公开(公告)号：US10891884B1

公开(公告)日：2021-01-12

申请号：US16281996

申请日：2019-02-21

Applicant: Apple Inc.

Inventor： Bo Yang ,  Xiang Lu ,  Andrew J. Copperhall ,  Henry C. Jen ,  Karthik Manickam ,  Sagar Nataraj ,  Shriram Vijayakumar ,  Derek K. Shaeffer

IPC: G09G3/00 ,  G09G3/32 ,  G01R31/3185 ,  G01R31/317 ,  G01R31/58

Abstract: Design-for-test (DFT) architectures, and methods of testing an array of chips, which may be identical, are described. In an embodiment, a comparison circuit includes a plurality of comparators to compare scan-data out (SDO) data streams with an expected data stream and transmit a compared data stream that is indicated of whether or not an error exists in any of the SDO data streams.