公开(公告)号：US12288066B1

公开(公告)日：2025-04-29

申请号：US18320036

申请日：2023-05-18

Applicant: Apple Inc.

Inventor： Zhaoxiang Jin ,  Francesco Spadini ,  Skanda K. Srinivasa ,  Milos Becvar

IPC: G06F9/30

Abstract: Techniques are disclosed that relate to fusing operations for execution of certain instructions. A processor may include a first execution circuit, of a first type, coupled to a first register file, a second execution circuit, of a second type, coupled to a second register file and a load/store circuit coupled to the first and second register files. The load/store circuit includes an issue port configured to receive an instruction operation for execution, a memory execution circuit configured to execute memory access operations, and a register transfer execution circuit. The register transfer execution circuit is configured to execute instruction operations specifying data transfer from the first register file to the second register file and an operation to be performed using the data, and the load/store circuit is configured to direct a given instruction operation from the issue port to one of the memory execution circuit or the register transfer execution circuit.

公开(公告)号：US20240329988A1

公开(公告)日：2024-10-03

申请号：US18739070

申请日：2024-06-10

Applicant: Apple Inc.

Inventor： John D. Pape ,  Skanda K. Srinivasa ,  Francesco Spadini ,  Brian T. Mokrzycki

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30043 ,  G06F9/3001 ,  G06F9/30058 ,  G06F9/3016 ,  G06F9/30185 ,  G06F9/3838 ,  G06F9/3858 ,  G06F9/3861

Abstract: Techniques are disclosed that relate to executing fused instructions. A processor may include a decoder circuit and a load/store circuit. The decoder circuit may detect a load/store instruction to load a value from a memory and detect a non-load/store instruction that depends on the value to be loaded. The decoder circuit may fuse the load/store instruction and the non-load/store instruction such that one or more operations that the non-load/store instruction is defined to perform are to be executed within the load/store circuit. The load/store circuit may receive an indication of the fused load/store and non-load/store instructions and then execute one or more operations of the load/store instruction and the one or more operations of the non-load/store instruction using a circuit included in the load/store circuit.

公开(公告)号：US12217060B1

公开(公告)日：2025-02-04

申请号：US18176457

申请日：2023-02-28

Applicant: Apple Inc.

Inventor： Francesco Spadini ,  Skanda K. Srinivasa ,  Reena Panda ,  Brian T. Mokrzycki ,  Haoyan Jia ,  Zhaoxiang Jin

IPC: G06F9/30

Abstract: Techniques are disclosed that relate to executing pairs of instructions. A processor may include fusion detector circuitry configured to detect a pair of fetched instructions and fuse the pair of fetched instructions into a fused instruction operation, and execution circuitry coupled to the fusion detector circuitry and configured to execute the fused instruction operation. In some embodiments the pair of instructions is executable to generate a remainder of a division operation. In some embodiments the pair of instructions is executable to compare two operands and perform a write operation based on the comparison. In some embodiments the pair of instructions is executable to perform an operation and apply a mask bit sequence to the result. The fusion detector circuitry may also be configured to obtain first and second portions of a constant value from first and second instructions and store the first and second portions in a destination register.

公开(公告)号：US12008369B1

公开(公告)日：2024-06-11

申请号：US17652501

申请日：2022-02-25

Applicant: Apple Inc.

Inventor： John D. Pape ,  Skanda K. Srinivasa ,  Francesco Spadini ,  Brian T. Mokrzycki

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30043 ,  G06F9/3001 ,  G06F9/30058 ,  G06F9/3016 ,  G06F9/30185 ,  G06F9/3838 ,  G06F9/3858 ,  G06F9/3861

Abstract: Techniques are disclosed that relate to executing fused instructions. A processor may include a decoder circuit and a load/store circuit. The decoder circuit may detect a load/store instruction to load a value from a memory and detect a non-load/store instruction that depends on the value to be loaded. The decoder circuit may fuse the load/store instruction and the non-load/store instruction such that one or more operations that the non-load/store instruction is defined to perform are to be executed within the load/store circuit. The load/store circuit may receive an indication of the fused load/store and non-load/store instructions and then execute one or more operations of the load/store instruction and the one or more operations of the non-load/store instruction using a circuit included in the load/store circuit.

公开(公告)号：US10120690B1

公开(公告)日：2018-11-06

申请号：US15181183

申请日：2016-06-13

Applicant: Apple Inc.

Inventor： Skanda K. Srinivasa ,  Jonathan Jay Tyler

IPC: G06F9/30 ,  G06F1/14

Abstract: Systems, apparatuses, and methods for pre-computing early age indicators for a non-shifting reservation station. A reservation station may include a plurality of entries storing a plurality of instruction operations prior to issuance to an execution unit. The reservation station may include control logic for pre-computing early age indicators for specifying which entry of each adjacent pair of entries is the oldest ready instruction operation. The early age indicators may be routed through registers and then through additional levels of control logic for determining the oldest ready instruction operation in all of the entries of the reservation station.