公开(公告)号：US20240329988A1

公开(公告)日：2024-10-03

申请号：US18739070

申请日：2024-06-10

Applicant: Apple Inc.

Inventor： John D. Pape ,  Skanda K. Srinivasa ,  Francesco Spadini ,  Brian T. Mokrzycki

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30043 ,  G06F9/3001 ,  G06F9/30058 ,  G06F9/3016 ,  G06F9/30185 ,  G06F9/3838 ,  G06F9/3858 ,  G06F9/3861

Abstract: Techniques are disclosed that relate to executing fused instructions. A processor may include a decoder circuit and a load/store circuit. The decoder circuit may detect a load/store instruction to load a value from a memory and detect a non-load/store instruction that depends on the value to be loaded. The decoder circuit may fuse the load/store instruction and the non-load/store instruction such that one or more operations that the non-load/store instruction is defined to perform are to be executed within the load/store circuit. The load/store circuit may receive an indication of the fused load/store and non-load/store instructions and then execute one or more operations of the load/store instruction and the one or more operations of the non-load/store instruction using a circuit included in the load/store circuit.

公开(公告)号：US20250094355A1

公开(公告)日：2025-03-20

申请号：US18544110

申请日：2023-12-18

Applicant: Apple Inc.

Inventor： Brett S. Feero ,  Brian T. Mokrzycki ,  Jonathan Y. Tong ,  Michael D. Snyder ,  James N. Hardage

IPC: G06F12/1027

Abstract: Techniques are disclosed relating to using an instruction (e.g., a pre-translate instruction) to lock translations in TLB entries. The execution of the instruction may include storing translation information in a TLB entry, and setting an indication that the entry is locked. The processor circuitry may receive an invalidate command corresponding to the locked entry. Processor circuitry may, in response to the invalidate command and based on the indication that the entry is locked, maintain the locked entry in a valid state in the translation lookaside buffer circuitry, notwithstanding the invalidate command. Processor circuitry may be further configured to modify previously-stored data in a given entry to aggregate, in the entry, translation information for multiple regions of the second address space.

公开(公告)号：US12217060B1

公开(公告)日：2025-02-04

申请号：US18176457

申请日：2023-02-28

Applicant: Apple Inc.

Inventor： Francesco Spadini ,  Skanda K. Srinivasa ,  Reena Panda ,  Brian T. Mokrzycki ,  Haoyan Jia ,  Zhaoxiang Jin

IPC: G06F9/30

Abstract: Techniques are disclosed that relate to executing pairs of instructions. A processor may include fusion detector circuitry configured to detect a pair of fetched instructions and fuse the pair of fetched instructions into a fused instruction operation, and execution circuitry coupled to the fusion detector circuitry and configured to execute the fused instruction operation. In some embodiments the pair of instructions is executable to generate a remainder of a division operation. In some embodiments the pair of instructions is executable to compare two operands and perform a write operation based on the comparison. In some embodiments the pair of instructions is executable to perform an operation and apply a mask bit sequence to the result. The fusion detector circuitry may also be configured to obtain first and second portions of a constant value from first and second instructions and store the first and second portions in a destination register.

公开(公告)号：US12008369B1

公开(公告)日：2024-06-11

申请号：US17652501

申请日：2022-02-25

Applicant: Apple Inc.

Inventor： John D. Pape ,  Skanda K. Srinivasa ,  Francesco Spadini ,  Brian T. Mokrzycki

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30043 ,  G06F9/3001 ,  G06F9/30058 ,  G06F9/3016 ,  G06F9/30185 ,  G06F9/3838 ,  G06F9/3858 ,  G06F9/3861

Abstract: Techniques are disclosed that relate to executing fused instructions. A processor may include a decoder circuit and a load/store circuit. The decoder circuit may detect a load/store instruction to load a value from a memory and detect a non-load/store instruction that depends on the value to be loaded. The decoder circuit may fuse the load/store instruction and the non-load/store instruction such that one or more operations that the non-load/store instruction is defined to perform are to be executed within the load/store circuit. The load/store circuit may receive an indication of the fused load/store and non-load/store instructions and then execute one or more operations of the load/store instruction and the one or more operations of the non-load/store instruction using a circuit included in the load/store circuit.