公开(公告)号：US20240036680A1

公开(公告)日：2024-02-01

申请号：US18323659

申请日：2023-05-25

Applicant: Apple Inc.

Inventor： Shinya Ono ,  Suhwan Moon ,  Dong-Gwang Ha ,  Jiaxi Hu ,  Hao-Lin Chiu ,  Kwang Soon Park ,  Hassan Edrees ,  Wen-I Hsieh ,  Jiun-Jye Chang ,  Chin-Wei Lin ,  Kyung Wook Kim

IPC: G06F3/041 ,  G09G3/3208 ,  G06F3/044

CPC classification number: G06F3/04184 ,  G06F3/0412 ,  G09G3/3208 ,  G06F3/0446 ,  G06F3/0444 ,  G06F2203/04107 ,  G06F2203/04112

Abstract: An electronic device may have a display with touch sensors. One or more shielding layers may be interposed between the display and the touch sensors. The display may include transistors with gate conductors, a first planarization layer formed over the gate conductors, one or more contacts formed in a first source-drain layer within the first planarization layer, a second planarization layer formed on the first planarization layer, one or more data lines formed in a second source-drain layer within the second planarization layer, a third planarization layer formed on the second planarization layer, and a data line shielding structure formed at least partly in a third source-drain layer within the third planarization layer. The data line shielding structure may be a routing line, a blanket layer, a mesh layer formed in one or more metal layers, and/or a data line covering another data line.

公开(公告)号：US11966544B2

公开(公告)日：2024-04-23

申请号：US18323659

申请日：2023-05-25

Applicant: Apple Inc.

Inventor： Shinya Ono ,  Suhwan Moon ,  Dong-Gwang Ha ,  Jiaxi Hu ,  Hao-Lin Chiu ,  Kwang Soon Park ,  Hassan Edrees ,  Wen-I Hsieh ,  Jiun-Jye Chang ,  Chin-Wei Lin ,  Kyung Wook Kim

IPC: G06F3/041 ,  G06F3/044 ,  G09G3/3208

CPC classification number: G06F3/04184 ,  G06F3/0412 ,  G06F3/0444 ,  G06F3/0446 ,  G09G3/3208 ,  G06F2203/04107 ,  G06F2203/04112

Abstract: An electronic device may have a display with touch sensors. One or more shielding layers may be interposed between the display and the touch sensors. The display may include transistors with gate conductors, a first planarization layer formed over the gate conductors, one or more contacts formed in a first source-drain layer within the first planarization layer, a second planarization layer formed on the first planarization layer, one or more data lines formed in a second source-drain layer within the second planarization layer, a third planarization layer formed on the second planarization layer, and a data line shielding structure formed at least partly in a third source-drain layer within the third planarization layer. The data line shielding structure may be a routing line, a blanket layer, a mesh layer formed in one or more metal layers, and/or a data line covering another data line.