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公开(公告)号：US20200272464A1
公开(公告)日：2020-08-27
申请号：US16818200
申请日：2020-03-13
Applicant: Apple Inc.
Inventor： Eric Bainville , Tal Uliel , Erik Norden , Jeffry E. Gonion , Ali Sazegari
Abstract: In an embodiment, a matrix computation engine is configured to perform matrix computations (e.g. matrix multiplications). The matrix computation engine may perform numerous matrix computations in parallel, in an embodiment. More particularly, the matrix computation engine may be configured to perform numerous multiplication operations in parallel on input matrix elements, generating resulting matrix elements. In an embodiment, the matrix computation engine may be configured to accumulate results in a result memory, performing multiply-accumulate operations for each matrix element of each matrix.
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公开(公告)号：US20190310854A1
公开(公告)日：2019-10-10
申请号：US15946719
申请日：2018-04-05
Applicant: Apple Inc.
Inventor： Eric Bainville , Tal Uliel , Jeffry E. Gonion , Ali Sazegari , Erik K. Norden
Abstract: In an embodiment, a computation engine may perform computations on input vectors having vector elements of a first precision and data type. The computation engine may convert the vector elements from the first precision to a second precision and may also interleave the vector elements as specified by an instruction issued by the processor to the computation engine. The interleave may be based on a ratio of a result precision and the second precision. An extract instruction may be supported to extract results from the computations and convert and deinterleave the vector elements to to provide a compact result in a desired order.
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公开(公告)号：US10990401B2
公开(公告)日：2021-04-27
申请号：US16837631
申请日：2020-04-01
Applicant: Apple Inc.
Inventor： Tal Uliel , Eric Bainville , Jeffry E. Gonion , Ali Sazegari
IPC: G06F9/302 , G06F9/312 , G06F15/76 , G06F17/16 , G06F7/52 , G06F9/38 , G06F15/80 , G06F9/30 , G06F7/544
Abstract: In an embodiment, a computation engine may perform dot product computations on input vectors. The dot product operation may have a first operand and a second operand, and the dot product may be performed on a subset of the vector elements in the first operand and each of the vector elements in the second operand. The subset of vector elements may be separated in the first operand by a stride that skips one or more elements between each element to which the dot product operation is applied. More particularly, in an embodiment, the input operands of the dot product operation may be a first vector having second vectors as elements, and the stride may select a specified element of each second vector.
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公开(公告)号：US10592239B2
公开(公告)日：2020-03-17
申请号：US16423702
申请日：2019-05-28
Applicant: Apple Inc.
Inventor： Eric Bainville , Tal Uliel , Erik Norden , Jeffry E. Gonion , Ali Sazegari
Abstract: In an embodiment, a matrix computation engine is configured to perform matrix computations (e.g. matrix multiplications). The matrix computation engine may perform numerous matrix computations in parallel, in an embodiment. More particularly, the matrix computation engine may be configured to perform numerous multiplication operations in parallel on input matrix elements, generating resulting matrix elements. In an embodiment, the matrix computation engine may be configured to accumulate results in a result memory, performing multiply-accumulate operations for each matrix element of each matrix.
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5.发明申请公开(公告)号：US20180121199A1
公开(公告)日：2018-05-03
申请号：US15629126
申请日：2017-06-21
Applicant: Apple Inc.
Inventor： Tal Uliel , Jeffry E. Gonion , Ali Sazegari , Eric Bainville
CPC classification number: G06F9/30036 , G06F7/483 , G06F7/485 , G06F7/4876 , G06F7/5443 , G06F9/30014
Abstract: In an embodiment, a processor may implement a fused multiply-add (FMA) instruction that accepts vector operands having vector elements with a first precision, and performing both the multiply and add operations at a higher precision. The add portion of the operation may add adjacent pairs of multiplication results from the multiply portion of the operation, which may allow the result to be stored in a vector register of the same overall length as the input vector registers but with fewer, higher precision vector elements, in an embodiment. Additionally, the overall operation may have high accuracy because of the higher precision throughout the operation.
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Patent Agency Ranking
公开(公告)号：US10970078B2
公开(公告)日：2021-04-06
申请号：US15946719
申请日：2018-04-05
Applicant: Apple Inc.
Inventor： Eric Bainville , Tal Uliel , Jeffry E. Gonion , Ali Sazegari , Erik K. Norden
Abstract: In an embodiment, a computation engine may perform computations on input vectors having vector elements of a first precision and data type. The computation engine may convert the vector elements from the first precision to a second precision and may also interleave the vector elements as specified by an instruction issued by the processor to the computation engine. The interleave may be based on a ratio of a result precision and the second precision. An extract instruction may be supported to extract results from the computations and convert and deinterleave the vector elements to provide a compact result in a desired order.
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公开(公告)号：US20190310855A1
公开(公告)日：2019-10-10
申请号：US15946724
申请日：2018-04-05
Applicant: Apple Inc.
Inventor： Tal Uliel , Eric Bainville , Jeffry E. Gonion , Ali Sazegari
IPC: G06F9/38
Abstract: In an embodiment, a computation engine may perform dot product computations on input vectors. The dot product operation may have a first operand and a second operand, and the dot product may be performed on a subset of the vector elements in the first operand and each of the vector elements in the second operand. The subset of vector elements may be separated in the first operand by a stride that skips one or more elements between each element to which the dot product operation is applied. More particularly, in an embodiment, the input operands of the dot product operation may be a first vector having second vectors as elements, and the stride may select a specified element of each second vector.
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公开(公告)号：US20200241876A1
公开(公告)日：2020-07-30
申请号：US16847068
申请日：2020-04-13
Applicant: Apple Inc.
Inventor： O-Cheng Chang , Tal Uliel , Eric Bainville , Jeffry E. Gonion , Ali Sazegari
Abstract: In an embodiment, a processor (e.g. a CPU) may offload transcendental computation to a computation engine that may efficiently perform transcendental functions. The computation engine may implement a range instruction that may be included in a program being executed by the CPU. The CPU may dispatch the range instruction to the computation engine. The range instruction may take an input operand (that is to be evaluated in a transcendental function, for example) and may reference a range table that defines a set of ranges for the transcendental function. The range instruction may identify one of the set of ranges that includes the input operand. For example, the range instruction may output an interval number identifying which interval of an overall set of valid input values contains the input operand. In an embodiment, the range instruction may take an input vector operand and output a vector of interval identifiers.
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公开(公告)号：US20200225958A1
公开(公告)日：2020-07-16
申请号：US16837631
申请日：2020-04-01
Applicant: Apple Inc.
Inventor： Tal Uliel , Eric Bainville , Jeffry E. Gonion , Ali Sazegari, PhD
IPC: G06F9/38
Abstract: In an embodiment, a computation engine may perform dot product computations on input vectors. The dot product operation may have a first operand and a second operand, and the dot product may be performed on a subset of the vector elements in the first operand and each of the vector elements in the second operand. The subset of vector elements may be separated in the first operand by a stride that skips one or more elements between each element to which the dot product operation is applied. More particularly, in an embodiment, the input operands of the dot product operation may be a first vector having second vectors as elements, and the stride may select a specified element of each second vector.
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公开(公告)号：US20190250917A1
公开(公告)日：2019-08-15
申请号：US15896582
申请日：2018-02-14
Applicant: Apple Inc.
Inventor： O-Cheng Chang , Tal Uliel , Eric Bainville , Jeffry E. Gonion , Ali Sazegari
CPC classification number: G06F9/30076 , G06F9/3004 , G06F9/3802
Abstract: In an embodiment, a computation engine may offload a processor (e.g. a CPU) and efficiently perform transcendental functions. The computation engine may implement a range instruction that may be included in a program being executed by the CPU. The CPU may dispatch the range instruction to the computation engine. The range instruction may take an input operand (that is to be evaluated in a transcendental function, for example) and may reference a range table that defines a set of ranges for the transcendental function. The range instruction may identify one of the set of ranges that includes the input operand. For example, the range instruction may output an interval number identifying which interval of an overall set of valid input values contains the input operand. In an embodiment, the range instruction may take an input vector operand and output a vector of interval identifiers.
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