公开(公告)号：US11636176B2

公开(公告)日：2023-04-25

申请号：US17085971

申请日：2020-10-30

Applicant: Apple Inc.

Inventor： William C. Athas ,  Zaid M. Nadeem ,  Tetiana Parshakova

IPC: G06F17/17 ,  G06F7/523 ,  G06F7/50

Abstract: An interpolation circuit included in a computer system may receive an operand that includes a plurality of bits occupying respective ones of a plurality of ordered bit positions, and generate multiple conditionally-negated values of respective portions of the operand starting at corresponding bit positions. The interpolation circuit may combine the operand and the plurality of conditionally-negated values to generate an approximation of a result of an arithmetic operation performed on the operand.

公开(公告)号：US20220100818A1

公开(公告)日：2022-03-31

申请号：US17085971

申请日：2020-10-30

Applicant: Apple Inc.

Inventor： William C. Athas ,  Zaid M. Nadeem ,  Tetiana Parshakova

IPC: G06F17/17 ,  G06F9/30 ,  G06F7/50 ,  G06F7/523

Abstract: An interpolation circuit included in a computer system may receive an operand that includes a plurality of bits occupying respective ones of a plurality of ordered bit positions, and generate multiple conditionally-negated values of respective portions of the operand starting at corresponding bit positions. The interpolation circuit may combine the operand and the plurality of conditionally-negated values to generate an approximation of a result of an arithmetic operation performed on the operand.