公开(公告)号：US12067188B2

公开(公告)日：2024-08-20

申请号：US18319223

申请日：2023-05-17

Applicant: Apple Inc.

Inventor： Jared L. Zerbe ,  Brian H. Tsang ,  Timothy M. Johnson ,  Bryan D. Raines ,  Zaid M. Nadeem ,  Andy J. Zhou ,  Xinhao Wang

IPC: G06F3/041

CPC classification number: G06F3/0416

Abstract: Sensing circuitry of a first electronic device can be configured to sense a signal transmitted by the second, external electronic device contacting and coupling through the body of the user. The first electronic device can be configured to detect the contact while receiving data from the second device, and determine whether the signal transmitted by the external device corresponds an “intentional touch,” or corresponds to a signal coupling between a different body part and the external device or through a different signal pathway (e.g., electromagnetically, through the air, etc.).

公开(公告)号：US11636176B2

公开(公告)日：2023-04-25

申请号：US17085971

申请日：2020-10-30

Applicant: Apple Inc.

Inventor： William C. Athas ,  Zaid M. Nadeem ,  Tetiana Parshakova

IPC: G06F17/17 ,  G06F7/523 ,  G06F7/50

Abstract: An interpolation circuit included in a computer system may receive an operand that includes a plurality of bits occupying respective ones of a plurality of ordered bit positions, and generate multiple conditionally-negated values of respective portions of the operand starting at corresponding bit positions. The interpolation circuit may combine the operand and the plurality of conditionally-negated values to generate an approximation of a result of an arithmetic operation performed on the operand.

公开(公告)号：US20220100818A1

公开(公告)日：2022-03-31

申请号：US17085971

申请日：2020-10-30

Applicant: Apple Inc.

Inventor： William C. Athas ,  Zaid M. Nadeem ,  Tetiana Parshakova

IPC: G06F17/17 ,  G06F9/30 ,  G06F7/50 ,  G06F7/523

Abstract: An interpolation circuit included in a computer system may receive an operand that includes a plurality of bits occupying respective ones of a plurality of ordered bit positions, and generate multiple conditionally-negated values of respective portions of the operand starting at corresponding bit positions. The interpolation circuit may combine the operand and the plurality of conditionally-negated values to generate an approximation of a result of an arithmetic operation performed on the operand.