公开(公告)号：US20240430138A1

公开(公告)日：2024-12-26

申请号：US18339232

申请日：2023-06-21

Applicant: Apple Inc.

Inventor： Charles L. Wang ,  Yi-Hsiu E. Chen ,  Yu-Yau Guo ,  Wei-Ming Lee

IPC: H04L25/02 ,  G06F13/40

Abstract: An apparatus for performing a fast common mode recharge is disclosed. The apparatus includes a transmitter circuit configured to transmit a differential signal on a communication bus that includes a true signal line and a complement signal line and a measurement circuit configured to measure respective voltage levels of the true signal line and the complement signal line. The apparatus further includes a control circuit configured to, in response to exiting a sleep mode, select one of a plurality of operation modes using the respective voltage levels of the true signal line and the complement signal line. The transmitter circuit is further configured to adjust the respective voltage levels of the true signal line and the complement signal line based on a selected operation mode of the plurality of operation modes.

公开(公告)号：US11063600B1

公开(公告)日：2021-07-13

申请号：US16929995

申请日：2020-07-15

Applicant: Apple Inc.

Inventor： Wenbo Liu ,  Wei-Ming Lee ,  Sanjeev K. Maheshwari

IPC: H03L7/099 ,  H03K3/03 ,  H03L7/191

Abstract: A multi-stage clock generation circuit is disclosed. The circuit includes first and second ring oscillators. The ring oscillators include a corresponding plurality of delay elements coupled in series, with a plurality of shunt circuits in parallel with corresponding inverters. The shunt circuits include respective interpolation nodes, which are resistively coupled to input and output nodes of their corresponding inverters. The interpolation nodes of the first ring oscillator are coupled to delay element input and output nodes of the second ring oscillator. Similarly, the interpolation nodes of the second ring oscillator are coupled to delay element input and output nodes of the first ring oscillator.