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    Duty cycle and skew measurement and correction for differential and single-ended clock signals
    1.
    发明授权
    Duty cycle and skew measurement and correction for differential and single-ended clock signals 有权

    公开(公告)号：US11165416B2

    公开(公告)日：2021-11-02

    申请号：US16701844

    申请日：2019-12-03

    Applicant: Apple Inc.

    Inventor： Khaled M. Alashmouny ,  Dennis M. Fischette, Jr. ,  Charles L. Wang ,  Samed Maltabas ,  Yikun Chang

    IPC: H03K5/156 ,  G06F1/10

    Abstract: A system and method for efficient on-chip monitoring of clock signals post-silicon. An electronic circuit includes a post-silicon and on-die signal monitor and a first signal generator that sends a first signal with a first signal period to the signal monitor. The signal monitor selects a first sampling signal with a first sampling period such that a ratio of the first sampling period to the first signal period is greater than one and is a non-integer. The signal monitor selects a reference voltage level for indicating when the first signal is asserted. When the first sampling period has elapsed, the signal monitor samples the first signal to generate a voltage level, and upon completing sampling, determines a duty cycle of the generated voltage levels, which indicates a duty cycle of the first signal. Using a similar approach, the signal monitor is also capable of determining skew between two signals.

    CODING FOR PULSE AMPLITUDE MODULATION WITH AN ODD NUMBER OF OUTPUT LEVELS
    2.
    发明公开
    CODING FOR PULSE AMPLITUDE MODULATION WITH AN ODD NUMBER OF OUTPUT LEVELS 审中-公开

    公开(公告)号：US20240305287A1

    公开(公告)日：2024-09-12

    申请号：US18664505

    申请日：2024-05-15

    Applicant: APPLE INC.

    Inventor： Charles L. Wang ,  Yi-Hsiu E. Chen ,  Pranavi Sunkara

    IPC: H03K9/02 ,  H03K7/02

    CPC classification number: H03K9/02 ,  H03K7/02

    Abstract: The present disclosure describes embodiments of driver circuit. The driver circuit includes a first impedance element electrically coupled to a first inverter circuit and a second impedance element electrically coupled to the first impedance element and a second inverter circuit. For a first encoding using the driver circuit, the first inverter circuit and the second inverter circuit are controlled such that a first current flows through the first and second impedance elements, the first current having a first value and a first direction. For a second encoding using the driver circuit, the first inverter circuit and the second inverter circuit are controlled such that a second current flows through the first and second impedance elements, the second current having a second value and a second direction. The first value is substantially the same as the second value and the first direction is opposite to the second direction.

    Coding for pulse amplitude modulation with an odd number of output levels
    3.
    发明授权
    Coding for pulse amplitude modulation with an odd number of output levels 有权

    公开(公告)号：US12015413B2

    公开(公告)日：2024-06-18

    申请号：US17945429

    申请日：2022-09-15

    Applicant: Apple Inc.

    Inventor： Charles L. Wang ,  Yi-Hsiu E. Chen ,  Pranavi Sunkara

    IPC: H03K9/02 ,  H03K7/02

    CPC classification number: H03K9/02 ,  H03K7/02

    Abstract: The present disclosure describes embodiments of driver circuit. The driver circuit includes a first impedance element electrically coupled to a first inverter circuit and a second impedance element electrically coupled to the first impedance element and a second inverter circuit. For a first encoding using the driver circuit, the first inverter circuit and the second inverter circuit are controlled such that a first current flows through the first and second impedance elements, the first current having a first value and a first direction. For a second encoding using the driver circuit, the first inverter circuit and the second inverter circuit are controlled such that a second current flows through the first and second impedance elements, the second current having a second value and a second direction. The first value is substantially the same as the second value and the first direction is opposite to the second direction.

    Fast Common Mode Charging
    4.
    发明申请
    Fast Common Mode Charging 有权

    公开(公告)号：US20240430138A1

    公开(公告)日：2024-12-26

    申请号：US18339232

    申请日：2023-06-21

    Applicant: Apple Inc.

    Inventor： Charles L. Wang ,  Yi-Hsiu E. Chen ,  Yu-Yau Guo ,  Wei-Ming Lee

    IPC: H04L25/02 ,  G06F13/40

    Abstract: An apparatus for performing a fast common mode recharge is disclosed. The apparatus includes a transmitter circuit configured to transmit a differential signal on a communication bus that includes a true signal line and a complement signal line and a measurement circuit configured to measure respective voltage levels of the true signal line and the complement signal line. The apparatus further includes a control circuit configured to, in response to exiting a sleep mode, select one of a plurality of operation modes using the respective voltage levels of the true signal line and the complement signal line. The transmitter circuit is further configured to adjust the respective voltage levels of the true signal line and the complement signal line based on a selected operation mode of the plurality of operation modes.

    DUTY CYCLE AND SKEW MEASUREMENT AND CORRECTION FOR DIFFERENTIAL AND SINGLE-ENDED CLOCK SIGNALS
    7.
    发明申请
    DUTY CYCLE AND SKEW MEASUREMENT AND CORRECTION FOR DIFFERENTIAL AND SINGLE-ENDED CLOCK SIGNALS 有权

    公开(公告)号：US20210167766A1

    公开(公告)日：2021-06-03

    申请号：US16701844

    申请日：2019-12-03

    Applicant: Apple Inc.

    Inventor： Khaled M. Alashmouny ,  Dennis M. Fischette, JR. ,  Charles L. Wang ,  Samed Maltabas

    IPC: H03K5/156 ,  G06F1/10

    Abstract: A system and method for efficient on-chip monitoring of clock signals post-silicon. An electronic circuit includes a post-silicon and on-die signal monitor and a first signal generator that sends a first signal with a first signal period to the signal monitor. The signal monitor selects a first sampling signal with a first sampling period such that a ratio of the first sampling period to the first signal period is greater than one and is a non-integer. The signal monitor selects a reference voltage level for indicating when the first signal is asserted. When the first sampling period has elapsed, the signal monitor samples the first signal to generate a voltage level, and upon completing sampling, determines a duty cycle of the generated voltage levels, which indicates a duty cycle of the first signal. Using a similar approach, the signal monitor is also capable of determining skew between two signals.

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