公开(公告)号：US20230388162A1

公开(公告)日：2023-11-30

申请号：US17804476

申请日：2022-05-27

Applicant: Apple Inc.

Inventor： Lizhi Zhong ,  Vishal Varma ,  Yu Chen ,  Wenyi Jin

IPC: H04L25/03 ,  H04B1/10

CPC classification number: H04L25/03267 ,  H04B1/10

Abstract: A receiver circuit including mechanisms for analog channel equalization and channel adaptation is disclosed. The receiver includes a front-end circuit configured to generate a filtered signal by performing filtering of an incoming signal that includes a stream of data symbols. A sample recovery circuit configured to sample an equalized signal, based on the filtered signal, to generate a plurality of recovered data symbols. A decision feedback equalization (DFE) circuit configured to generate the feedback signal based on the plurality of recovered data symbols. A logic circuit is configured to cause adjustment to one or more filters in the front-end circuit based on the plurality of recovered data symbols.

公开(公告)号：US20240179034A1

公开(公告)日：2024-05-30

申请号：US18402011

申请日：2024-01-02

Applicant: Apple Inc.

Inventor： Lizhi Zhong ,  Vishal Varma ,  Yu Chen ,  Wenyi Jin

IPC: H04L25/03 ,  H04B1/10

CPC classification number: H04L25/03267 ,  H04B1/10

Abstract: A receiver circuit including mechanisms for analog channel equalization and channel adaptation is disclosed. The receiver includes a front-end circuit configured to generate a filtered signal by performing filtering of an incoming signal that includes a stream of data symbols. A sample recovery circuit configured to sample an equalized signal, based on the filtered signal, to generate a plurality of recovered data symbols. A decision feedback equalization (DFE) circuit configured to generate the feedback signal based on the plurality of recovered data symbols. A logic circuit is configured to cause adjustment to one or more filters in the front-end circuit based on the plurality of recovered data symbols.

公开(公告)号：US11902059B2

公开(公告)日：2024-02-13

申请号：US17804476

申请日：2022-05-27

Applicant: Apple Inc.

Inventor： Lizhi Zhong ,  Vishal Varma ,  Yu Chen ,  Wenyi Jin

IPC: H04B1/10 ,  H04L25/03

CPC classification number: H04L25/03267 ,  H04B1/10

Abstract: A receiver circuit including mechanisms for analog channel equalization and channel adaptation is disclosed. The receiver includes a front-end circuit configured to generate a filtered signal by performing filtering of an incoming signal that includes a stream of data symbols. A sample recovery circuit configured to sample an equalized signal, based on the filtered signal, to generate a plurality of recovered data symbols. A decision feedback equalization (DFE) circuit configured to generate the feedback signal based on the plurality of recovered data symbols. A logic circuit is configured to cause adjustment to one or more filters in the front-end circuit based on the plurality of recovered data symbols.