-
公开(公告)号：US20230388100A1
公开(公告)日：2023-11-30
申请号：US18152492
申请日：2023-01-10
Applicant: Apple Inc.
Inventor： Hairong Yu , Boon-Aik Ang , Yu Chen , Litesh Sajnani , Samed Maltabas , Shaobo Liu , Gregory N. Santos , Richard Y. Su , Meei-Ling Chiang , Pyoungwon Park , Dennis M. Fischette, JR.
CPC classification number: H04L7/0337 , H04L7/0331 , H03L7/093
Abstract: A clock generator circuit may include a multiplex circuit and a phase-locked loop circuit. The multiplex circuit may generate a reference clock signal for the phase-locked loop circuit by selecting one of different clock signals. In response to a switch of the reference clock signal from one clock signal to another, the phase-locked loop circuit may disable phase-locking and enter into a frequency acquisition mode during which the frequency of the phase-locked loop circuit's output clock signal is adjusted based on the frequency of the newly selected reference clock signal. After a period of time has elapsed, the phase-locked loop circuit returns to phase-locking operation.
-
公开(公告)号：US10939387B2
公开(公告)日：2021-03-02
申请号：US16381946
申请日：2019-04-11
Applicant: Apple Inc.
Inventor： Digvijay Arjunrao Jadhav , Indranil S. Sen , Jonathan C. King , Mohit Narang , Prathyusha Sangepu , Qiong Wu , Shrenik Milapchand , Vijay Gadde , Yu Chen
IPC: H04W52/26
Abstract: Multi-radio wireless network devices are capable of transmitting and/or receiving data from multiple radiofrequency (RF) networks at different bands. Total transmission power limitations may be in place due to, for example, safety reasons. As a result, active management of transmission power may be performed during simultaneous transmission in different bands and/or networks. In some embodiments, the management may take place on group-by-group basis and a network-by-network basis. Antennas may be grouped based on their relative positions and impact on radiation emitted by the devices.
-
公开(公告)号：US12160497B2
公开(公告)日：2024-12-03
申请号：US18152492
申请日：2023-01-10
Applicant: Apple Inc.
Inventor： Hairong Yu , Boon-Aik Ang , Yu Chen , Litesh Sajnani , Samed Maltabas , Shaobo Liu , Gregory N. Santos , Richard Y. Su , Meei-Ling Chiang , Pyoungwon Park , Dennis M Fischette, Jr.
Abstract: A clock generator circuit may include a multiplex circuit and a phase-locked loop circuit. The multiplex circuit may generate a reference clock signal for the phase-locked loop circuit by selecting one of different clock signals. In response to a switch of the reference clock signal from one clock signal to another, the phase-locked loop circuit may disable phase-locking and enter into a frequency acquisition mode during which the frequency of the phase-locked loop circuit's output clock signal is adjusted based on the frequency of the newly selected reference clock signal. After a period of time has elapsed, the phase-locked loop circuit returns to phase-locking operation.
-
公开(公告)号：US11902059B2
公开(公告)日：2024-02-13
申请号：US17804476
申请日：2022-05-27
Applicant: Apple Inc.
Inventor： Lizhi Zhong , Vishal Varma , Yu Chen , Wenyi Jin
CPC classification number: H04L25/03267 , H04B1/10
Abstract: A receiver circuit including mechanisms for analog channel equalization and channel adaptation is disclosed. The receiver includes a front-end circuit configured to generate a filtered signal by performing filtering of an incoming signal that includes a stream of data symbols. A sample recovery circuit configured to sample an equalized signal, based on the filtered signal, to generate a plurality of recovered data symbols. A decision feedback equalization (DFE) circuit configured to generate the feedback signal based on the plurality of recovered data symbols. A logic circuit is configured to cause adjustment to one or more filters in the front-end circuit based on the plurality of recovered data symbols.
-
公开(公告)号：US11115037B1
公开(公告)日：2021-09-07
申请号：US17018968
申请日：2020-09-11
Applicant: Apple Inc.
Inventor： Samed Maltabas , Boon-Aik Ang , Yu Chen , Dennis M. Fischette, Jr.
Abstract: A clock signal generated by a fractional-N phase-locked loop circuit may include deterministic jitter resulting from a sigma-delta modulation of a frequency divisor used by a divider circuit. In order to reduce such jitter, a cancelation circuit is employed that can generate a feedback signal by delaying an output signal from the divider circuit, where the amount of delay applied to the output signal is based on an accumulated phase residue from the modulation of the frequency divisor. The resultant feedback signal is compared to a reference signal, results of which are used to adjust an oscillator circuit generating the clock signal, thereby reducing the deterministic jitter.
-
Patent Agency Ranking
公开(公告)号：US11031945B1
公开(公告)日：2021-06-08
申请号：US17019028
申请日：2020-09-11
Applicant: Apple Inc.
Inventor： Samed Maltabas , Yu Chen , Dennis M. Fischette, Jr.
Abstract: A phase-locked loop circuit included in a computer system includes time-to-digital converter and digital-to-time converter circuits. During a mode to test the time-to-digital converter circuit, the digital-to-time converter circuit is coupled to the time-to-digital converter circuit in a loop-back fashion. A control circuit supplies stimulus codes to the digital-time-converter circuit, which generates multiple delayed versions of a reference clock signal using the stimulus codes. The time-to-digital converter circuit, in turn, generates capture codes based on the delay between the reference clock signal and the delayed versions of the reference clock signal. The control circuit compares the capture codes to the stimulus codes to determine a linearity of a response of the time-to-digital converter circuit.
-
公开(公告)号：US20240179034A1
公开(公告)日：2024-05-30
申请号：US18402011
申请日：2024-01-02
Applicant: Apple Inc.
Inventor： Lizhi Zhong , Vishal Varma , Yu Chen , Wenyi Jin
CPC classification number: H04L25/03267 , H04B1/10
Abstract: A receiver circuit including mechanisms for analog channel equalization and channel adaptation is disclosed. The receiver includes a front-end circuit configured to generate a filtered signal by performing filtering of an incoming signal that includes a stream of data symbols. A sample recovery circuit configured to sample an equalized signal, based on the filtered signal, to generate a plurality of recovered data symbols. A decision feedback equalization (DFE) circuit configured to generate the feedback signal based on the plurality of recovered data symbols. A logic circuit is configured to cause adjustment to one or more filters in the front-end circuit based on the plurality of recovered data symbols.
-
公开(公告)号：US11825422B2
公开(公告)日：2023-11-21
申请号：US17188585
申请日：2021-03-01
Applicant: Apple Inc.
Inventor： Digvijay Arjunrao Jadhav , Indranil S. Sen , Jonathan C. King , Mohit Narang , Prathyusha Sangepu , Qiong Wu , Shrenik Milapchand , Vijay Gadde , Yu Chen
IPC: H04W52/26
CPC classification number: H04W52/26
Abstract: Multi-radio wireless network devices are capable of transmitting and/or receiving data from multiple radiofrequency (RF) networks at different bands. Total transmission power limitations may be in place due to, for example, safety reasons. As a result, active management of transmission power may be performed during simultaneous transmission in different bands and/or networks. In some embodiments, the management may take place on group-by-group basis and a network-by-network basis. Antennas may be grouped based on their relative positions and impact on radiation emitted by the devices.
-
9.发明授权公开(公告)号：US11256283B2
公开(公告)日：2022-02-22
申请号：US16736776
申请日：2020-01-07
Applicant: Apple Inc.
Inventor： Meei-Ling Chiang , Dabin Zhang , Dennis M. Fischette, Jr. , Shaobo Liu , Yu Chen , Samed Maltabas
Abstract: Systems, apparatuses, and methods for implementing a hybrid asynchronous gray counter with a non-gray zone detector are described. A circuit includes an asynchronous gray counter coupled to control logic. The control logic programs the asynchronous gray counter to operate in different modes to perform various functions associated with a high-performance phase-locked loop (PLL). In a first mode, the asynchronous gray counter serves as a frequency detector to count oscillator cycles within a reference clock cycle. In a second mode, the asynchronous gray counter serves as a coarse phase detector to detect a phase error between a feedback clock and a reference clock. In a third mode, the asynchronous gray counter serves as a multi-modulus divider to divide an oscillator clock down to create a feedback clock. Using a single asynchronous gray counter for three separate functions reduces power consumption and area utilization.
-
公开(公告)号：US10556252B2
公开(公告)日：2020-02-11
申请号：US15846809
申请日：2017-12-19
Applicant: Apple Inc.
Inventor： Lok Pui Calvin Tsang , Yu Chen , Qingguo Zhao , Weiqiang Fu , Hong Feng Wang , Chung Yin Au
Abstract: An electronic device includes an enclosure, a display positioned with the enclosure and defining a front face of the electronic device, and a haptic actuator positioned within the enclosure. The haptic actuator includes a housing comprising a wall and a movable mass positioned within the housing and configured to move within the housing to cause the haptic actuator to produce a vibrational response. The vibrational response includes a first component within a frequency range and a second component outside of the frequency range and providing a haptic output portion of the vibrational response. The haptic actuator also includes a tuning feature incorporated with the wall and configured to reduce the first component of the vibrational response while substantially maintaining the haptic output portion of the vibrational response.
-
-
-
-
-
-
-
-
-
Search Results
14
records
(took 0.017 seconds)
