公开(公告)号：US20240096263A1

公开(公告)日：2024-03-21

申请号：US18353584

申请日：2023-07-17

Applicant: Apple Inc.

Inventor： Denis M. Darmon ,  Christopher P. Tann ,  Hopil Bae ,  Yanghyo Kim ,  Ramana V. Rachakonda ,  Xiaofeng Wang ,  Robert D. Zucker

IPC: G09G3/20 ,  G02B26/08

CPC classification number: G09G3/2096 ,  G02B26/0833 ,  G09G2320/0626 ,  G09G2330/021 ,  G09G2360/18

Abstract: A device may include image processing circuitry that generates image data corresponding to an image to be displayed during a first image frame and a second image frame. However, the image data is not regenerated for the second image frame. The device may also include an electronic display having a frame buffer that receives and stores the image data from the image processing circuitry. The electronic display may also include a display panel that displays the image during the first image frame based on a first read of the image data from the frame buffer in response to a first emission sync signal and displays the image during the second image frame based on a second read of the image data from the frame buffer in response to a second emission sync signal.

公开(公告)号：US20240304163A1

公开(公告)日：2024-09-12

申请号：US18119772

申请日：2023-03-09

Applicant: Apple Inc.

Inventor： Yung-Chin Chen ,  Hopil Bae ,  Mahdi Farrokh Baroughi ,  Sheng Zhang ,  Yanghyo Kim ,  Young Don Bae

IPC: G09G5/12 ,  G09G5/18

CPC classification number: G09G5/12 ,  G09G5/18 ,  G09G2320/041 ,  G09G2320/0673 ,  G09G2340/0435

Abstract: An electronic device uses a leader synchronize signal generator to synchronize clock signal generators used by multiple components in the electronic device to a common time-base. A processor core complex of the electronic device sends per-frame configuration to a timing controller for frames to be displayed on an electronic display before a corresponding frame begins.