公开(公告)号：US20250040186A1

公开(公告)日：2025-01-30

申请号：US18227275

申请日：2023-07-27

Applicant: Applied Materials, Inc.

Inventor： Yan ZHANG ,  Taegon KIM ,  Johannes M. VAN MEER ,  Vikram M. BHOSLE ,  Jae Young LEE ,  Naushad K. VARIAM

IPC: H01L29/423 ,  H01L21/768 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786

Abstract: Approaches herein provide devices and methods for forming gate-all-around transistors with improved gate spacer k-values. One method may include forming a gate-all-around (GAA) stack including a plurality of alternating first layers and second layers, and forming a source/drain (S/D) cavity through the plurality of alternating first layers and second layers. The method may further include forming an inner spacer in the S/D cavity, adjacent the plurality of alternating first layers and second layers, performing a first implant by directing fluorine ions to the GAA stack, through the S/D cavity, wherein the first implant is performed at a temperature greater than 30° Celsius and forming a S/D material in the S/D cavity following the first implant.