公开(公告)号：US20240079273A1

公开(公告)日：2024-03-07

申请号：US18389517

申请日：2023-11-14

Applicant: Applied Materials, Inc.

Inventor： Jungrae Park ,  ZAVIER ZAI YEONG TAN ,  KARTHIK BALAKRISHNAN ,  JAMES S. PAPANU ,  WEI-SHENG LEI

IPC: H01L21/78 ,  H01L21/67

CPC classification number: H01L21/78 ,  H01L21/67069 ,  H01L21/67115 ,  H01L21/02071

Abstract: An embodiment disclosed herein includes a method of dicing a wafer comprising a plurality of integrated circuits. In an embodiment, the method comprises forming a mask above the semiconductor wafer, and patterning the mask and the semiconductor wafer with a first laser process. The method may further comprise patterning the mask and the semiconductor wafer with a second laser process, where the second laser process is different than the first laser process. In an embodiment, the method may further comprise etching the semiconductor wafer with a plasma etching process to singulate the integrated circuits.