公开(公告)号：US08972806B2

公开(公告)日：2015-03-03

申请号：US13654833

申请日：2012-10-18

Applicant: Applied Micro Circuits Corporation

Inventor： Glen Miller

IPC: G01R31/28 ,  G01R31/3177 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/3171 ,  G01R31/31715

Abstract: Providing for testing of digital sequencing components of an integrated chip is described herein. By way of example, self-test procedures are provided for unidirectional integrated chips that have different sequence generation (e.g., transmission) and sequence monitoring (e.g., receiving) frequencies. A test logic component(s) can be added to an integrated chip to match the sequence generation frequency to the sequence monitoring frequency. This can facilitate self-testing of unidirectional sequence generating components, by modifying a generated sequence at a first datarate to be receivable at a second datarate, and directing the modified sequence to sequence monitoring components of the integrated chip configured to operate at the second datarate.

Abstract translation: 本文描述了对集成芯片的数字排序组件的测试。 作为示例，为具有不同序列生成（例如，传输）和序列监视（例如，接收）频率的单向集成芯片提供自检程序。 可以将测试逻辑组件添加到集成芯片以将序列产生频率与序列监视频率相匹配。 这可以通过修改在第二数据位可接收的第一数据位上产生的序列，以及将经修改的序列引导到被配置为在第二数据位上操作的集成芯片的序列监视组件，从而促进单向序列生成组件的自检。

公开(公告)号：US20140115409A1

公开(公告)日：2014-04-24

申请号：US13654833

申请日：2012-10-18

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Glen Miller

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/3171 ,  G01R31/31715

Abstract: Providing for testing of digital sequencing components of an integrated chip is described herein. By way of example, self-test procedures are provided for unidirectional integrated chips that have different sequence generation (e.g., transmission) and sequence monitoring (e.g., receiving) frequencies. A test logic component(s) can be added to an integrated chip to match the sequence generation frequency to the sequence monitoring frequency. This can facilitate self-testing of unidirectional sequence generating components, by modifying a generated sequence at a first datarate to be receivable at a second datarate, and directing the modified sequence to sequence monitoring components of the integrated chip configured to operate at the second datarate.

Abstract translation: 本文描述了对集成芯片的数字排序组件的测试。 作为示例，为具有不同序列生成（例如，传输）和序列监视（例如，接收）频率的单向集成芯片提供自检程序。 可以将测试逻辑组件添加到集成芯片以将序列生成频率与序列监视频率相匹配。 这可以通过修改在第二数据位可接收的第一数据位上产生的序列，以及将经修改的序列引导到被配置为在第二数据位上操作的集成芯片的序列监视组件，从而促进单向序列生成组件的自检。