公开(公告)号：US20240256281A1

公开(公告)日：2024-08-01

申请号：US18101726

申请日：2023-01-26

Applicant: Arm Limited

Inventor： Quentin Éric NOUVEL ,  Luca NASSI ,  Adrien PESLE

IPC: G06F9/38

CPC classification number: G06F9/384

Abstract: A data processing apparatus comprises: execution circuitry to execute instructions in order to perform data processing operations specified by those instructions; a plurality of registers to store data values for access by the execution circuitry when performing the data processing operations, each register having an associated physical register identifier; register rename circuitry to select physical register identifiers to associate with architectural register identifiers specified by the instructions; and rename storage having a plurality of entries, each entry being associated with one of the architectural register identifiers and used by the register rename circuitry to indicate a physical register identifier selected for association with that one of the architectural register identifiers; the register rename circuitry comprising an execute unit, and being responsive to detection of an early execute condition for a given instruction, the early execute condition requiring at least detection that each source value required to execute the given instruction is available to the register rename circuitry without accessing the plurality of registers, to cause the execute unit to perform the data processing operation specified by the given instruction in order to generate a result value, and to cause the generated result value to be stored in an entry of the rename storage associated with a destination architectural register identifier specified by the given instruction.

公开(公告)号：US20190278709A1

公开(公告)日：2019-09-12

申请号：US15912659

申请日：2018-03-06

Applicant: Arm Limited

Inventor： Lucas GARCIA ,  Laurent Claude DESNOGUES ,  Adrien PESLE ,  Vincenzo CONSALES

IPC: G06F12/0862

Abstract: Data processing circuitry comprises a processing element to execute successive iterations of program code to access a set of data elements in memory, each iteration accessing one or more respective data elements of the set; a data element structure memory to store a memory address relationship between the data elements of the set; and prefetch circuitry, responsive to an access by a current program code iteration to a current data element of the set, to detect, using the memory address relationship stored in the data element structure memory a memory address defining a subsequent data element to be accessed by a next program iteration and to initiate prefetching of at least a portion of the subsequent data element from memory.