公开(公告)号：US20230195468A1

公开(公告)日：2023-06-22

申请号：US17557583

申请日：2021-12-21

Applicant: Arm Limited

Inventor： Houdhaifa BOUZGUARROU ,  Guillaume BOLBENES ,  Thibaut Elie LANOIS ,  Vincenzo CONSALES ,  Chang Joo LEE

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3806 ,  G06F9/3844 ,  G06F9/3005

Abstract: An apparatus has a fetch queue to identify a sequence of instructions to be fetched for execution and prediction circuitry to predict upcoming control flow and to control which instructions are identified in the fetch queue in dependence on the prediction. The prediction circuitry predicts multi-taken sequences which are sequences of instructions in which control flow is diverted by a first control flow changing instruction to a series of instructions terminating in a second control flow changing instruction that diverts control flow to a target address. The apparatus also has prediction confidence calculation circuitry to calculate confidence levels for respective multi-taken sequences. Each confidence level is indicative of a confidence in an accuracy of prediction of its respective multi-taken sequence. When the confidence level for a particular multi-taken sequence satisfies a prediction confidence condition, the prediction confidence tracking circuitry allows the particular multi-taken sequence to be predicted by the prediction circuitry. The prediction circuitry causes the series of instructions and the target instruction for the particular multi-taken sequence to be identified in the fetch queue when the prediction circuitry predicts the particular multi-taken sequence and further predictions to be made starting from the target address for the particular multi-taken sequence.

公开(公告)号：US20200057643A1

公开(公告)日：2020-02-20

申请号：US16105028

申请日：2018-08-20

Applicant: Arm Limited

Inventor： Houdhaifa BOUZGUARROU ,  Guillaume BOLBENES ,  Vincenzo CONSALES

IPC: G06F9/38

Abstract: An apparatus and method are provided for performing branch prediction. The apparatus has processing circuitry for executing instructions out-of-order with respect to original program order, and event counting prediction circuitry for maintaining event count values for branch instructions, for use in making branch outcome predictions for those branch instructions. Further, checkpointing storage stores state information of the apparatus at a plurality of checkpoints to enable the state information to be restored for a determined one of those checkpoints in response to a flush event. The event counting prediction circuitry has training storage with a first number of training entries, each training entry being associated with a branch instruction. The event counting prediction circuitry implements a training phase for each training entry during which it seeks to determine an event count value for the associated branch instruction based on branch outcome behaviour of the branch instruction observed for instances of execution of the branch instruction that have been committed by the processing circuitry. The event counting prediction circuitry further has access storage with a second number of active entries, where the second number is less than the first number. Each active entry is associated with a branch instruction for which an event count value has been successfully determined during the training phase. The event counting prediction circuitry is arranged to make branch outcome predictions for branch instructions having an active entry. At each checkpoint, state information for the active entries is stored to the checkpointing storage. This provides a particularly efficient form of event counting prediction circuitry that can be used in out-of-order systems, while reducing the amount of state information that needs to stored into the checkpointing storage at each checkpoint.

公开(公告)号：US20230135599A1

公开(公告)日：2023-05-04

申请号：US17512888

申请日：2021-10-28

Applicant: Arm Limited

Inventor： Paolo MONTI ,  Abdel Hadi MOUSTAFA ,  Albin Pierrick TONNERRE ,  Vincenzo CONSALES ,  ABHISHEK RAJA

IPC: G06F12/1027

Abstract: Circuitry comprises a translation lookaside buffer to store memory address translations, each memory address translation being between an input memory address range defining a contiguous range of one or more input memory addresses in an input memory address space and a translated output memory address range defining a contiguous range of one or more output memory addresses in an output memory address space; in which the translation lookaside buffer is configured selectively to store the memory address translations as a cluster of memory address translations, a cluster defining memory address translations in respect of a contiguous set of input memory address ranges by encoding one or more memory address offsets relative to a respective base memory address; memory management circuitry to retrieve data representing memory address translations from a memory, for storage by the translation lookaside buffer, when a required memory address translation is not stored by the translation lookaside buffer; detector circuitry to detect an action consistent with access, by the translation lookaside buffer, to a given cluster of memory address translations; and prefetch circuitry, responsive to a detection of the action consistent with access to a cluster of memory address translations, to prefetch data from the memory representing one or more further memory address translations of a further set of input memory address ranges adjacent to the contiguous set of input memory address ranges for which the given cluster defines memory address translations.

公开(公告)号：US20190278709A1

公开(公告)日：2019-09-12

申请号：US15912659

申请日：2018-03-06

Applicant: Arm Limited

Inventor： Lucas GARCIA ,  Laurent Claude DESNOGUES ,  Adrien PESLE ,  Vincenzo CONSALES

IPC: G06F12/0862

Abstract: Data processing circuitry comprises a processing element to execute successive iterations of program code to access a set of data elements in memory, each iteration accessing one or more respective data elements of the set; a data element structure memory to store a memory address relationship between the data elements of the set; and prefetch circuitry, responsive to an access by a current program code iteration to a current data element of the set, to detect, using the memory address relationship stored in the data element structure memory a memory address defining a subsequent data element to be accessed by a next program iteration and to initiate prefetching of at least a portion of the subsequent data element from memory.

公开(公告)号：US20190196833A1

公开(公告)日：2019-06-27

申请号：US15852065

申请日：2017-12-22

Applicant: Arm Limited

Inventor： Houdhaifa BOUZGUARROU ,  Guillaume BOLBENES ,  Vincenzo CONSALES ,  Eddy LAPEYRE

IPC: G06F9/38 ,  G06F9/30

Abstract: Data processing circuitry comprises fetch circuitry to fetch blocks, containing instructions for execution, defined by a fetch queue; and prediction circuitry to predict one or more next blocks to be fetched and to add the predicted next blocks to the fetch queue; the prediction circuitry comprising: branch prediction circuitry to detect a predicted branch destination for a branch instruction in a current block, the predicted branch destination representing either a branch target for a branch predicted to be taken or a next instruction after the branch instruction, for a branch predicted not to be taken; and sequence prediction circuitry to detect sequence data, associated with the predicted branch destination, identifying a next block following the predicted branch destination in the program flow order having a next instance of a branch instruction, to add to the fetch queue the identified next block and any intervening blocks between the current block and the identified next block, and to initiate branch prediction in respect of the predicted next instance of a branch instruction.