公开(公告)号：US11775380B2

公开(公告)日：2023-10-03

申请号：US17156443

申请日：2021-01-22

Applicant: Arm Limited

Inventor： Nicholas John Nelson Murphy ,  Jussi Tuomas Pennala ,  Andreas Adamidis ,  Benjamin Charles James

IPC: G06F11/10 ,  G06F12/0804

CPC classification number: G06F11/1004 ,  G06F12/0804 ,  G06F2212/1008

Abstract: A data processing system comprises a memory, a processing unit, a MMU operable to process memory transactions for the processing unit; and an error-detecting circuit located between the MMU and the memory. The MMU is configured to determine from respective memory address mappings corresponding memory addresses to which memory transaction applies. The determined memory addresses comprise a first part representing a memory location and a second part representing an error-detecting code generated using the first part of the memory address. The error-detecting circuit can then check using the error-detecting code for the memory address whether the memory address received by the error-detecting circuit is valid.

公开(公告)号：US20220147416A1

公开(公告)日：2022-05-12

申请号：US17156443

申请日：2021-01-22

Applicant: Arm Limited

Inventor： Nicholas John Nelson Murphy ,  Jussi Tuomas Pennala ,  Andreas Adamidis ,  Benjamin Charles James

IPC: G06F11/10 ,  G06F12/0804

Abstract: A data processing system comprises a memory, a processing unit, a MMU operable to process memory transactions for the processing unit; and an error-detecting circuit located between the MMU and the memory. The MMU is configured to determine from respective memory address mappings corresponding memory addresses to which memory transaction applies. The determined memory addresses comprise a first part representing a memory location and a second part representing an error-detecting code generated using the first part of the memory address. The error-detecting circuit can then check using the error-detecting code for the memory address whether the memory address received by the error-detecting circuit is valid.