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公开(公告)号：US11775380B2
公开(公告)日：2023-10-03
申请号：US17156443
申请日：2021-01-22
Applicant: Arm Limited
Inventor： Nicholas John Nelson Murphy , Jussi Tuomas Pennala , Andreas Adamidis , Benjamin Charles James
IPC: G06F11/10 , G06F12/0804
CPC classification number: G06F11/1004 , G06F12/0804 , G06F2212/1008
Abstract: A data processing system comprises a memory, a processing unit, a MMU operable to process memory transactions for the processing unit; and an error-detecting circuit located between the MMU and the memory. The MMU is configured to determine from respective memory address mappings corresponding memory addresses to which memory transaction applies. The determined memory addresses comprise a first part representing a memory location and a second part representing an error-detecting code generated using the first part of the memory address. The error-detecting circuit can then check using the error-detecting code for the memory address whether the memory address received by the error-detecting circuit is valid.
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公开(公告)号：US12282794B2
公开(公告)日：2025-04-22
申请号：US18251564
申请日：2021-11-04
Applicant: Arm Limited
Inventor： David Thomas Garbett , Jussi Tuomas Pennala , Henrik Nils-Sture Olsson , Nicholas John Nelson Murphy
Abstract: A data processing system (1) comprises a plurality of processing units (11) and a controller (30) operable to allocate processing units of the plurality of processing units into respective groups of the processing units, wherein each group of processing units comprises a set of one or more of the processing units of the plurality of processing units. The data processing system further comprises an arbiter (31, 32) for each group of processing units for controlling access by virtual machines (33, 34) that require processing operations to the processing units of the group of processing units that the arbiter has been allocated.
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公开(公告)号：US11907056B2
公开(公告)日：2024-02-20
申请号：US17455609
申请日：2021-11-18
Applicant: Arm Limited
Inventor： Eamonn Quigley , Nicholas John Nelson Murphy , Jussi Tuomas Pennala , Henrik Nils-Sture Olsson
CPC classification number: G06F11/079 , G06F11/0766 , G06F11/1479 , G06F11/3668 , G06T1/20
Abstract: Disclosed herein is a data processing system comprising a processing unit operable to process data to generate a sequence of outputs, wherein the processing unit is configurable, when generating a sequence of outputs, such that the data processing for generating an output in the sequence of outputs will be performed within a respective processing period for the output. A controller for the processing unit is configured to cause the processing unit, when generating a sequence of outputs, during a respective processing period for at least one output in the sequence of outputs, to also undergo one or more fault detection test(s) such that both processing of data for the output and fault detection testing is performed during the respective processing period for the output.
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公开(公告)号：US20220147416A1
公开(公告)日：2022-05-12
申请号：US17156443
申请日：2021-01-22
Applicant: Arm Limited
Inventor： Nicholas John Nelson Murphy , Jussi Tuomas Pennala , Andreas Adamidis , Benjamin Charles James
IPC: G06F11/10 , G06F12/0804
Abstract: A data processing system comprises a memory, a processing unit, a MMU operable to process memory transactions for the processing unit; and an error-detecting circuit located between the MMU and the memory. The MMU is configured to determine from respective memory address mappings corresponding memory addresses to which memory transaction applies. The determined memory addresses comprise a first part representing a memory location and a second part representing an error-detecting code generated using the first part of the memory address. The error-detecting circuit can then check using the error-detecting code for the memory address whether the memory address received by the error-detecting circuit is valid.
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