公开(公告)号：US10784842B2

公开(公告)日：2020-09-22

申请号：US16239498

申请日：2019-01-03

Applicant: Arm Limited

Inventor： Seshagiri Rao Bogi ,  Vinay Chenani ,  Biswanath Nayak ,  Vijaya Kumar Vinukonda

IPC: H03K3/02 ,  H03K19/094 ,  H03K19/018 ,  H03K5/003

Abstract: Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has first transistors arranged as a diode, a first latch and feedback assist to facilitate shifting an input voltage in a first voltage domain to an output voltage in a second voltage domain. The first stage uses the diode and the first latch to reduce contention between the first latch and input transistors. The diode, the first latch and the feedback assist enable activation of the input transistors with the input voltage. The second stage has second transistors arranged as a second latch followed by output buffers that provide a buffered output voltage as feedback to the feedback assist of the first stage.

公开(公告)号：US20200220529A1

公开(公告)日：2020-07-09

申请号：US16239498

申请日：2019-01-03

Applicant: Arm Limited

Inventor： Seshagiri Rao Bogi ,  Vinay Chenani ,  Biswanath Nayak ,  Vijaya Kumar Vinukonda

IPC: H03K3/02 ,  H03K5/003 ,  H03K19/018 ,  H03K19/094

Abstract: Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has first transistors arranged as a diode, a first latch and feedback assist to facilitate shifting an input voltage in a first voltage domain to an output voltage in a second voltage domain. The first stage uses the diode and the first latch to reduce contention between the first latch and input transistors. The diode, the first latch and the feedback assist enable activation of the input transistors with the input voltage. The second stage has second transistors arranged as a second latch followed by output buffers that provide a buffered output voltage as feedback to the feedback assist of the first stage.