公开(公告)号：US11923844B2

公开(公告)日：2024-03-05

申请号：US17731846

申请日：2022-04-28

Applicant: Arm Limited

Inventor： Seshagiri Rao Bogi ,  Vinay Chenani ,  Gurupadayya Shidaganti ,  Akshaykumar V Jabi

IPC: H03K19/0185 ,  H03K3/356 ,  H03K17/081 ,  H03K19/003 ,  H03K19/007

CPC classification number: H03K19/007 ,  H03K3/356113 ,  H03K17/08104 ,  H03K19/00315

Abstract: Various implementations described herein are related to a device having a level shifter that receives an input signal and reference voltages and provides level-shifted input signals based on the reference voltages. The device may have a pre-driver that receives the level-shifted input signals and reference voltages and provides gate voltages based on the reference voltages. The device may have a gate stabilizer that receives the reference voltages and provides a stabilized reference voltage based on the reference voltages. The device may have an output driver that receives the reference voltages, receives the gate voltages, receives the stabilized reference voltage and provides an output pad voltage to an input-output pad based on the reference voltages, the gate voltages and the stabilized reference voltage.

公开(公告)号：US10784842B2

公开(公告)日：2020-09-22

申请号：US16239498

申请日：2019-01-03

Applicant: Arm Limited

Inventor： Seshagiri Rao Bogi ,  Vinay Chenani ,  Biswanath Nayak ,  Vijaya Kumar Vinukonda

IPC: H03K3/02 ,  H03K19/094 ,  H03K19/018 ,  H03K5/003

Abstract: Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has first transistors arranged as a diode, a first latch and feedback assist to facilitate shifting an input voltage in a first voltage domain to an output voltage in a second voltage domain. The first stage uses the diode and the first latch to reduce contention between the first latch and input transistors. The diode, the first latch and the feedback assist enable activation of the input transistors with the input voltage. The second stage has second transistors arranged as a second latch followed by output buffers that provide a buffered output voltage as feedback to the feedback assist of the first stage.

公开(公告)号：US11169590B2

公开(公告)日：2021-11-09

申请号：US16517216

申请日：2019-07-19

Applicant: Arm Limited

Inventor： Ranabir Dey ,  Vinay Chenani ,  Kundan Srivastava ,  Vijaya Kumar Vinukonda

IPC: G06F1/00 ,  G06F1/3234 ,  G06F1/3225 ,  G06F1/3203

Abstract: Various implementations described herein are directed to a device having an output pad that provides an input-output (IO) voltage from an IO power supply. The device may include core ramp detection circuitry that detects a first ramp of a core voltage from a core power supply and provides a core ramp sensing signal. The device may include output logic circuitry that couples the output pad to ground after receiving the core ramp sensing signal so as to reduce leakage of the IO power supply.

公开(公告)号：US20230353150A1

公开(公告)日：2023-11-02

申请号：US17731846

申请日：2022-04-28

Applicant: Arm Limited

Inventor： Seshagiri Rao Bogi ,  Vinay Chenani ,  Gurupadayya Shidaganti ,  Akshaykumar V Jabi

IPC: H03K19/007 ,  H03K19/003 ,  H03K3/356 ,  H03K17/081

CPC classification number: H03K19/007 ,  H03K19/00315 ,  H03K3/356113 ,  H03K17/08104

Abstract: Various implementations described herein are related to a device having a level shifter that receives an input signal and reference voltages and provides level-shifted input signals based on the reference voltages. The device may have a pre-driver that receives the level-shifted input signals and reference voltages and provides gate voltages based on the reference voltages. The device may have a gate stabilizer that receives the reference voltages and provides a stabilized reference voltage based on the reference voltages. The device may have an output driver that receives the reference voltages, receives the gate voltages, receives the stabilized reference voltage and provides an output pad voltage to an input-output pad based on the reference voltages, the gate voltages and the stabilized reference voltage.

公开(公告)号：US20210018974A1

公开(公告)日：2021-01-21

申请号：US16517216

申请日：2019-07-19

Applicant: Arm Limited

Inventor： Ranabir Dey ,  Vinay Chenani ,  Kundan Srivastava ,  Vijaya Kumar Vinukonda

IPC: G06F1/3234 ,  G06F1/3225

Abstract: Various implementations described herein are directed to a device having an output pad that provides an input-output (IO) voltage from an IO power supply. The device may include core ramp detection circuitry that detects a first ramp of a core voltage from a core power supply and provides a core ramp sensing signal. The device may include output logic circuitry that couples the output pad to ground after receiving the core ramp sensing signal so as to reduce leakage of the IO power supply.

公开(公告)号：US20250047273A1

公开(公告)日：2025-02-06

申请号：US18229006

申请日：2023-08-01

Applicant: Arm Limited

Inventor： Seshagiri Rao Bogi ,  Gurupadayya Shidaganti ,  Vinay Chenani ,  Fabrice Blanc

IPC: H03K17/06 ,  H03K17/10 ,  H03K19/003

Abstract: Various implementations described herein are directed to a device having an input-output stage with first transistors coupled between a voltage supply and ground. Also, the device may have a power clamping stage with resistor-capacitor circuitry coupled in parallel with second transistors between the voltage supply and ground. Also, during a power surging event, electro-static discharge is distributed across the first transistors and the second transistors by way of passing from the voltage supply to ground.

公开(公告)号：US20220038101A1

公开(公告)日：2022-02-03

申请号：US17021393

申请日：2020-09-15

Applicant: Arm Limited

Inventor： Seshagiri Rao Bogi ,  Gayathri Gandhi ,  Vinay Chenani ,  Fabrice Blanc

IPC: H03K19/0185 ,  H03K19/17784 ,  H03K3/356

Abstract: A level down shifter circuit includes a latch and an assist circuit. The latch is configured to generate a digital shifted signal and a complementary shifted signal by a voltage downshift of a digital input signal and a complementary input signal. The digital input signal and the complementary input signal are in a first voltage domain. The digital shifted signal and the complementary shifted signal are in a second voltage domain. The second voltage domain has a smaller voltage range than the first voltage domain. The assist circuit is configured to alternately pull the digital shifted signal and the complementary shifted signal to an intermediate voltage in response to the digital input signal and the complementary input signal. The intermediate voltage is in the second voltage domain.

公开(公告)号：US11239842B1

公开(公告)日：2022-02-01

申请号：US17021393

申请日：2020-09-15

Applicant: Arm Limited

Inventor： Seshagiri Rao Bogi ,  Gayathri Gandhi ,  Vinay Chenani ,  Fabrice Blanc

IPC: H03K19/0185 ,  H03K3/356 ,  H03K19/17784

Abstract: A level down shifter circuit includes a latch and an assist circuit. The latch is configured to generate a digital shifted signal and a complementary shifted signal by a voltage downshift of a digital input signal and a complementary input signal. The digital input signal and the complementary input signal are in a first voltage domain. The digital shifted signal and the complementary shifted signal are in a second voltage domain. The second voltage domain has a smaller voltage range than the first voltage domain. The assist circuit is configured to alternately pull the digital shifted signal and the complementary shifted signal to an intermediate voltage in response to the digital input signal and the complementary input signal. The intermediate voltage is in the second voltage domain.

公开(公告)号：US20200220529A1

公开(公告)日：2020-07-09

申请号：US16239498

申请日：2019-01-03

Applicant: Arm Limited

Inventor： Seshagiri Rao Bogi ,  Vinay Chenani ,  Biswanath Nayak ,  Vijaya Kumar Vinukonda

IPC: H03K3/02 ,  H03K5/003 ,  H03K19/018 ,  H03K19/094

Abstract: Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has first transistors arranged as a diode, a first latch and feedback assist to facilitate shifting an input voltage in a first voltage domain to an output voltage in a second voltage domain. The first stage uses the diode and the first latch to reduce contention between the first latch and input transistors. The diode, the first latch and the feedback assist enable activation of the input transistors with the input voltage. The second stage has second transistors arranged as a second latch followed by output buffers that provide a buffered output voltage as feedback to the feedback assist of the first stage.