公开(公告)号：US12052508B2

公开(公告)日：2024-07-30

申请号：US18323768

申请日：2023-05-25

Applicant: Arm Limited

Inventor： Daniel Fedai Larsen ,  Tord Kvestad Øygard ,  Frank Klaeboe Langtind ,  Andreas Due Engh-Halstvedt

IPC: H04N23/73 ,  G06T5/92

CPC classification number: H04N23/73 ,  G06T5/92 ,  G06T2207/20172

Abstract: A method of processing data in a graphics processor when performing tile-based rendering in which a render output is sub-divided into a plurality of tiles for rendering. The rendering is performed as two separate processing passes: a first processing pass that sorts primitives into respective regions of the render output and a second processing pass that renders the tiles into which the render output is sub-divided for rendering. During the first processing pass, “tile elimination” data is generated indicative of which of the rendering tiles should be rendered during the second processing pass. The tile elimination data generated in the first processing pass can then be used to control the rendering of tiles during the second processing pass.