公开(公告)号：US11734869B2

公开(公告)日：2023-08-22

申请号：US17511032

申请日：2021-10-26

Applicant: Arm Limited

Inventor： Andreas Due Engh-Halstvedt ,  Frank Klaeboe Langtind ,  Mark Underwood

IPC: G06T1/60 ,  G06T15/00 ,  G06T15/80 ,  G06T1/20

CPC classification number: G06T15/005 ,  G06T1/20 ,  G06T1/60 ,  G06T15/80

Abstract: A method of operating a graphics processor that executes a graphics processing pipeline comprising a vertex shading stage is disclosed. A set of blocks of memory space that may be represented by a linked list is provided and memory space for storing vertex shaded attribute data generated by the vertex shading stage is allocated from one of the blocks of memory space in the set of blocks of memory space. When data stored in a block of memory space is no longer needed by the graphics processing pipeline, the block can be “recycled” for use by the pipeline.

公开(公告)号：US20220245751A1

公开(公告)日：2022-08-04

申请号：US17163289

申请日：2021-01-29

Applicant: Arm Limited

Inventor： Frank Klaeboe Langtind ,  Andreas Due Engh-Halstvedt

IPC: G06T1/20 ,  G06T11/20 ,  G06T1/60

Abstract: When generating a graphics processing output, a sequence of one or more of primitives to be processed when generating the output is assembled from a set of vertex indices provided for the output based on primitive configuration information provided for the output, each assembled primitive of the sequence of assembled primitives comprising an identifier for the primitive and a set of one or more vertex indices for the primitive. One or more attributes for vertices of the assembled primitives are then shaded and fetched based on the vertex indices of the assembled primitives. The assembled primitives including their shaded fetched vertex attribute(s) are then provided to later stages of the graphics processing pipeline for processing.

公开(公告)号：US20240169464A1

公开(公告)日：2024-05-23

申请号：US18499029

申请日：2023-10-31

Applicant: Arm Limited

Inventor： Frank Klaeboe Langtind ,  Andreas Due Engh-Halstvedt

IPC: G06T1/20 ,  G06T11/40

CPC classification number: G06T1/20 ,  G06T11/40

Abstract: When generating a graphics processing output by assembling a sequence of one or more of primitives to be processed from a set of vertex indices provided for the output based on primitive configuration information provided for the output, one or more vertex packets are generated using the vertex indices for the assembled primitives, each vertex packet comprising a plurality of vertices of the assembled primitives. After a threshold number of vertices have been allocated to a vertex packet, vertex attribute processing for the vertices of the vertex packet is triggered, to thereby generate a vertex packet comprising processed vertex attributes for the vertices of the vertex packet. The assembled primitives and the generated vertex packets are then provided to later stages of the graphics processing pipeline for processing.

公开(公告)号：US11941740B2

公开(公告)日：2024-03-26

申请号：US17511261

申请日：2021-10-26

Applicant: Arm Limited

Inventor： Michael Martin Klock ,  Philip Carlos Garcia ,  Frank Klaeboe Langtind ,  Peter Anthony Hearne

IPC: G06T1/20 ,  G06T1/60 ,  G06T15/00

CPC classification number: G06T15/005 ,  G06T1/20 ,  G06T1/60

Abstract: Disclosed subject matter relates generally to graphics processing, and relates more particularly to processing graphics vertex content.

公开(公告)号：US20230298249A1

公开(公告)日：2023-09-21

申请号：US18184094

申请日：2023-03-15

Applicant: Arm Limited

Inventor： Wei Shao ,  Frank Klaeboe Langtind

IPC: G06T15/00

CPC classification number: G06T15/005

Abstract: When performing tile-based graphics processing, a first vertex shading operation to generate vertex shaded position data for vertices is performed, and the vertex shaded position data used to prepare primitive lists indicating which primitives should be rendered for respective rendering tiles. Then, when processing a tile, a second vertex shading operation is performed for vertices of primitives for the tile for which fragments have been generated by a rasteriser prior to rendering the graphics fragments, to generate vertex shaded non-position attribute data for the vertices, based on the results of early depth testing before the fragments are rendered.

公开(公告)号：US10650580B2

公开(公告)日：2020-05-12

申请号：US16026402

申请日：2018-07-03

Applicant: Arm Limited

Inventor： Andreas Due Engh-Halstvedt ,  Frank Klaeboe Langtind

IPC: G06T15/80 ,  G06T1/60 ,  G06T15/00 ,  G06T1/20

Abstract: A graphics processing pipeline includes: a position shader, a tiler, a pool of memory for storing primitive lists and vertex shaded attributes data for vertices, a varying-only vertex shader, and a fragment frontend and shader. The position shader performs vertex shading for the positional attributes of the vertices of a set of vertices to be processed by the graphics processing pipeline. The tiler uses the vertex shaded position data to identify primitives that should be processed further to generate the render output. When the tiler determines that a vertex should be processed further to generate the render output, it allocates memory space in the memory pool for storing vertex shaded attributes data for the vertex. Vertex shaded attributes data for the vertex is then stored in the allocated space in the memory pool for later use, e.g., by the fragment frontend and shader.

公开(公告)号：US20190012829A1

公开(公告)日：2019-01-10

申请号：US16026402

申请日：2018-07-03

Applicant: Arm Limited

Inventor： Andreas Due Engh-Halstvedt ,  Frank Klaeboe Langtind

IPC: G06T15/80 ,  G06T1/60 ,  G06T1/20 ,  G06T15/00

Abstract: A graphics processing pipeline includes: a position shader, a tiler, a pool of memory for storing primitive lists and vertex shaded attributes data for vertices, a varying-only vertex shader, and a fragment frontend and shader. The position shader performs vertex shading for the positional attributes of the vertices of a set of vertices to be processed by the graphics processing pipeline. The tiler uses the vertex shaded position data to identify primitives that should be processed further to generate the render output. When the tiler determines that a vertex should be processed further to generate the render output, it allocates memory space in the memory pool for storing vertex shaded attributes data for the vertex. Vertex shaded attributes data for the vertex is then stored in the allocated space in the memory pool for later use, e.g., by the fragment frontend and shader.

公开(公告)号：US20250131653A1

公开(公告)日：2025-04-24

申请号：US18918872

申请日：2024-10-17

Applicant: Arm Limited

Inventor： Frank Klaeboe Langtind

IPC: G06T17/20 ,  G06T17/00

Abstract: A tile-based graphics processor performs first and second processing passes to generate a render output. The first processing pass generates and writes out information representative of a set of bounding boxes, and the second processing pass uses the bounding box information to determine which primitives to process for which rendering tiles.

公开(公告)号：US12052508B2

公开(公告)日：2024-07-30

申请号：US18323768

申请日：2023-05-25

Applicant: Arm Limited

Inventor： Daniel Fedai Larsen ,  Tord Kvestad Øygard ,  Frank Klaeboe Langtind ,  Andreas Due Engh-Halstvedt

IPC: H04N23/73 ,  G06T5/92

CPC classification number: H04N23/73 ,  G06T5/92 ,  G06T2207/20172

Abstract: A method of processing data in a graphics processor when performing tile-based rendering in which a render output is sub-divided into a plurality of tiles for rendering. The rendering is performed as two separate processing passes: a first processing pass that sorts primitives into respective regions of the render output and a second processing pass that renders the tiles into which the render output is sub-divided for rendering. During the first processing pass, “tile elimination” data is generated indicative of which of the rendering tiles should be rendered during the second processing pass. The tile elimination data generated in the first processing pass can then be used to control the rendering of tiles during the second processing pass.

公开(公告)号：US20240193718A1

公开(公告)日：2024-06-13

申请号：US18503916

申请日：2023-11-07

Applicant: Arm Limited

Inventor： Daren Croxford ,  Frank Klaeboe Langtind ,  Robert William Genders

IPC: G06T1/20 ,  G06T17/10

CPC classification number: G06T1/20 ,  G06T17/10

Abstract: A tiled-based graphics processor that comprises a plurality of tiling units is disclosed. The graphics processor includes an assigning circuit that assigns tiling units to sort geometry for initial regions of a render output that encompass plural primitive listing regions, and causes assigned tiling units to sort geometry for an initial region into primitive listing regions that the initial region encompasses.