公开(公告)号：US20250021480A1

公开(公告)日：2025-01-16

申请号：US18350217

申请日：2023-07-11

Applicant: Arm Limited

Inventor： Natalya BONDARENKO ,  Stefano GHIGGINI ,  Kamil GARIFULLIN ,  Fabian GRUBER ,  . ABHISHEK RAJA ,  Devin S. LAFFORD

IPC: G06F12/0811 ,  G06F12/0862 ,  G06F12/0871

Abstract: Apparatuses, methods, systems, and chip-containing products are disclosed, which relate to an arrangement comprising a level N cache level and a level M cache level, where M is greater than N. The level N cache level comprises a plurality of linefill slots and performs a slot allocation procedure in response to a lookup miss in dependence on a linefill slot occupancy criterion. The slot allocation procedure comprises allocation of an available slot of the plurality of slots to a pending linefill request generated in response to the lookup miss. The level N cache level effects a modification of the slot allocation procedure in dependence on the linefill slot occupancy criterion and is responsive to the linefill slot occupancy criterion being fulfilled to cause a linefill delegation action to be instructed to the level M cache level.

公开(公告)号：US20250021483A1

公开(公告)日：2025-01-16

申请号：US18350135

申请日：2023-07-11

Applicant: Arm Limited

Inventor： Scott Courtland HADLEY ,  Devin S. LAFFORD ,  Alexander Cole SHULYAK

IPC: G06F12/0862

Abstract: Aspects of the present disclosure relate to an apparatus comprising prefetch pattern storage circuitry and pattern training circuitry. The pattern training circuitry detects patterns of data access for updating one or more corresponding pattern storage entries. The pattern training circuitry comprises a plurality of training entries, associated with a given accessed storage location. Each said training entry comprises a plurality of regions. For a given training entry, at least one region is configured to store information for which a subsequent access offset is positive, and at least one region is configured to store information for which said offset is negative. The pattern training circuitry is configured to transmit data indicative of said information to the prefetch pattern storage circuitry. The prefetch pattern storage circuitry is responsive to receiving said transmitted data to update at least one corresponding pattern storage element.