公开(公告)号：US20210365764A1

公开(公告)日：2021-11-25

申请号：US16879587

申请日：2020-05-20

Applicant: Arm Limited

Inventor： Mbou Eyole ,  Shidhartha Das ,  Femando Garcia Redondo

IPC: G06N3/063 ,  G06N3/04

Abstract: Various implementations are related to an apparatus with memory cells arranged in columns and rows, and the memory cells are accessible with a column control voltage for accessing the memory cells via the columns and a row control voltage for accessing the memory cells via the rows. The apparatus may include neural network circuitry having neuronal junctions that are configured to receive, record, and provide information related to incoming voltage spikes associated with input signals based on resistance through the neuronal junctions. The apparatus may include stochastic re-programmer circuitry that receives the incoming voltage spikes, receives the information provided by the neuronal junctions, and reconfigure the information recorded in the neuronal junctions based on the incoming voltage spikes associated with the input signals along with a programming control signal provided by the memory circuitry.

公开(公告)号：US20220172762A1

公开(公告)日：2022-06-02

申请号：US17107725

申请日：2020-11-30

Applicant: Arm Limited

Inventor： Supreet Jeloka ,  Mudit Bhargava ,  Pranay Prabhat ,  Femando Garcia Redondo

IPC: G11C11/16

Abstract: Various implementations described herein are related to a method. The method may apply a write control voltage to a bitcell. The method may gradually ramp the write control voltage to the bitcell. The method may terminate application of the write control voltage to the bitcell when a write operation is sensed in the bitcell.