公开(公告)号：US20190004977A1

公开(公告)日：2019-01-03

申请号：US15638524

申请日：2017-06-30

Applicant: ARM LIMITED

Inventor： Carlo Dario FANARA ,  Frederic Jean Denis ARSANTO ,  Guillaume SCHON ,  Jocelyn Francois Orion JAUBERT

IPC: G06F12/14 ,  G06F9/44 ,  G06F9/24 ,  G06F1/24 ,  G06F9/30

Abstract: An apparatus has processing circuitry to perform data processing in one of two or more operating states associated with different levels of privilege. At least one operating state holding element holds a state indication indicating a current operating state of the processing circuitry. In response to a transition of a reset signal from a first value to a second value for triggering a reset of the processing circuitry, the at least one operating state holding element resets the state indication to indicate a default operating state other than a most privileged operating state of the two or more operating states.

公开(公告)号：US20140215189A1

公开(公告)日：2014-07-31

申请号：US13752621

申请日：2013-01-29

Applicant: ARM LIMITED

Inventor： Cedric Denis Robert AIRAUD ,  Luca SCALABRINO ,  Frederic Jean Denis ARSANTO ,  Guillaume SCHON ,  Frederic Claude Marie PIRY ,  Albin Pierick TONNERRE

IPC: G06F9/30

CPC classification number: G06F9/3836 ,  G06F9/30014 ,  G06F9/30196

Abstract: An apparatus and method includes execution circuitry including a wide operand execution unit configured to allow up to N bits of operand data to be processed during execution of a single instruction. Decoder circuitry decodes and generates, for each instruction, at least one control data block identifying an operation to be performed by the execution circuitry and at least two re-combineable control data blocks for the instruction. Issue queue control circuitry then allocates a slot in the issue queue for each of the at least two data blocks and up to M bits of associated operand data, and marks those allocated slots to identify that they contain re-combineable control data blocks. The issue queue control circuitry issues the combined block to said wide operand execution unit along with the operand data contained in each of the allocated slots for said at least two control data blocks.

Abstract translation: 一种装置和方法包括执行电路，其包括宽操作数执行单元，其被配置为允许在单个指令的执行期间处理最多N位的操作数数据。 解码器电路针对每个指令对至少一个控制数据块进行解码并生成至少一个控制数据块，该控制数据块标识由执行电路执行的操作和用于该指令的至少两个可重新组合的控制数据块。 发出队列控制电路然后为发送队列中的每个至少两个数据块和相关操作数数据的高达M位分配一个时隙，并标记这些分配的时隙以标识它们包含可重新组合的控制数据块。 所述问题队列控制电路与包含在所述至少两个控制数据块的所分配的时隙中的操作数数据一起向所述宽操作数执行单元发出组合块。

公开(公告)号：US20160335085A1

公开(公告)日：2016-11-17

申请号：US15076889

申请日：2016-03-22

Applicant: ARM LIMITED

Inventor： Luca SCALABRINO ,  Frederic Jean Denis ARSANTO ,  Thomas Gilles TARRIDEC ,  Cedric Denis Robert AIRAUD

IPC: G06F9/30

CPC classification number: G06F9/30087 ,  G06F8/458 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3877 ,  G06F9/522

Abstract: A data processing system 2 includes multiple out-of-order issue queues 8, 10. A master serialisation instruction MSI received by a first issue queue 8 is detected by slave generation circuitry 24 which generates a slave serialisation instruction SSI added to a second issue queue 10. The master serialisation instruction MSI manages serialisation relative to the instructions within the first issue queue 8. The slave serialisation instruction SSI manages serialisation relative to the instructions within the second issue queue 10. The master serialisation instruction MSI and the slave serialisation instruction SSI are removed when both have met their serialisation conditions and are respectively the oldest instructions within their issue queues.

Abstract translation: 数据处理系统2包括多个无序发行队列8,10。由第一发行队列8接收的主序列化指令MSI由从属产生电路24检测，该生成电路产生附加到第二发行队列的从串行化指令SSI 主序列化指令MSI管理相对于第一个问题队列8内的指令的串行化。从串行化指令SSI管理相对于第二个发布队列10内的指令的串行化。主序列化指令MSI和从串行化指令SSI是 当两者都满足其序列化条件并分别是其问题队列中的最早的指令时被移除。

公开(公告)号：US20140195780A1

公开(公告)日：2014-07-10

申请号：US13737137

申请日：2013-01-09

Applicant: ARM LIMITED

Inventor： Nicolas CHAUSSADE ,  Luca SCALABRINO ,  Frederic Jean Denis ARSANTO ,  Cedric Denis Robert AIRAUD

IPC: G06F9/38

CPC classification number: G06F9/3867 ,  G06F9/30072 ,  G06F9/3826

Abstract: A data processing apparatus comprises first and second processing circuitry. A conditional instruction executed by the second processing circuitry may have an outcome which is dependent on one of a plurality of sets of condition information maintained by the first processing circuitry. A first forwarding path can forward the sets of condition information from the first processing circuitry to a predetermined pipeline stage of a processing pipeline of the second processing circuitry. A request path can transmit a request signal from the second processing circuitry to the first processing circuitry, the request signal indicating a requested set of condition information which was not yet valid when a conditional instruction was at the predetermined pipeline stage. A second forwarding path may forward the requested set of condition information to a subsequent pipeline stage when the information becomes valid.

Abstract translation: 数据处理装置包括第一和第二处理电路。 由第二处理电路执行的条件指令可以具有取决于由第一处理电路维护的多组条件信息之一的结果。 第一转发路径可将来自第一处理电路的条件信息集合转发到第二处理电路的处理流水线的预定流水线级。 请求路径可以将来自第二处理电路的请求信号发送到第一处理电路，该请求信号指示当条件指令处于预定流水线阶段时尚未有效的请求的条件信息集合。 当信息变得有效时，第二转发路径可以将所请求的条件信息集合转发到后续流水线级。

公开(公告)号：US20210232396A1

公开(公告)日：2021-07-29

申请号：US16773059

申请日：2020-01-27

Applicant: Arm Limited

Inventor： Frederic Jean Denis ARSANTO ,  Carlo Dario FANARA ,  Luca SCALABRINO ,  Jean Sébastien LEROY

IPC: G06F9/30 ,  G06F9/38

Abstract: An apparatus and method are provided for inhibiting instruction manipulation. The apparatus has execution circuitry for performing data processing operations in response to a sequence of instructions from an instruction set, and decoder circuitry for decoding each instruction in the sequence in order to generate control signals for the execution circuitry. Each instruction comprises a plurality of instruction bits, and the decoder circuitry is arranged to perform a decode operation on each instruction to determine from the value of each instruction bit, and knowledge of the instruction set, the control signals to be issued to the execution circuitry in response to that instruction. An input path to the decoder circuitry comprises a set of wires over which the instruction bits of each instruction are provided. Scrambling circuitry is used to perform a scrambling function on each instruction using a secret scrambling key, such that the wire within the set of wires over which any given instruction bit is provided to the decoder circuitry is dependent on the secret scrambling key. The decode operation performed by the decoder circuitry is then adapted to incorporate a descrambling function using the secret scrambling key to reverse the effect of the scrambling function. As a result, independent of which wire any given instruction bit is provided on, the decode operation is arranged when decoding a given instruction to correctly interpret each instruction bit of that given instruction, based on knowledge of the instruction set, in order to determine from the value of each instruction bit the control signals to be issued to the execution circuitry in response to that given instruction.

公开(公告)号：US20190018686A1

公开(公告)日：2019-01-17

申请号：US15651158

申请日：2017-07-17

Applicant: ARM LIMITED

Inventor： Jocelyn Francois Orion JAUBERT ,  Frederic Jean Denis ARSANTO ,  Guillaume SCHON ,  Carlo Dario FANARA

IPC: G06F9/38 ,  G06F9/30

Abstract: An apparatus comprising: a set of registers; and mapping circuitry to perform a mapping operation to map each of a set of register specifiers to a respective register from among the set of registers in dependence on a mapping function. The mapping function is dependent on a key value. In addition, the mapping for at least two register specifiers from among the set of register specifiers is dependent on the same key value.

公开(公告)号：US20160335088A1

公开(公告)日：2016-11-17

申请号：US15082601

申请日：2016-03-28

Applicant: ARM LIMITED

Inventor： Luca SCALABRINO ,  Frederic Jean Denis ARSANTO ,  Thomas Gilles TARRIDEC ,  Cedric Denis Robert AIRAUD

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/384 ,  G06F9/3857

Abstract: A data processing apparatus comprises register rename circuitry for mapping architectural register specifiers specified by instructions to physical registers to be accessed in response to the instructions. Available register control circuitry controls which physical registers are available for mapping to an architectural register specifier by the register rename circuitry. For at least one group of two or more physical registers, the available register control circuitry controls availability of the registers based on a group tracking indication indicative of whether there is at least one pending access to any of the physical registers in the group.

Abstract translation: 数据处理装置包括寄存器重命名电路，用于将由指令指定的体系结构寄存器指定符映射到要响应于指令进行访问的物理寄存器。 可用的寄存器控制电路控制哪些物理寄存器可用于通过寄存器重命名电路映射到架构寄存器说明符。 对于至少一组两个或更多个物理寄存器，可用的寄存器控制电路基于组跟踪指示来控制寄存器的可用性，所述组跟踪指示指示是否存在至少一个待访问组中的任何物理寄存器。

公开(公告)号：US20190121967A1

公开(公告)日：2019-04-25

申请号：US15793186

申请日：2017-10-25

Applicant: ARM Limited

Inventor： Guillaume SCHON ,  Frederic Jean Denis ARSANTO ,  Carlo Dario FANARA ,  Jocelyn François Orion JAUBERT

IPC: G06F21/55 ,  G06F11/30 ,  G06F9/30

Abstract: Data processing circuitry comprises a set of two or more computational units to perform respective computational operations; an instruction decoder to decode successive data processing instructions and, for a given data processing instruction, to control one or more of the computational units to perform those computational operations required to execute the given data processing instruction; and control circuitry responsive to the given data processing instruction, to control one or more others of the computational units to perform further computational operations, other than the computational operations required to execute the given data processing instruction, during execution of the given data processing instruction.

公开(公告)号：US20190012267A1

公开(公告)日：2019-01-10

申请号：US16018438

申请日：2018-06-26

Applicant: ARM Limited

Inventor： Luca SCALABRINO ,  Frederic Jean Denis ARSANTO ,  Claire AUPETIT

IPC: G06F12/0862 ,  G06F9/38 ,  G06F9/30

Abstract: An apparatus and method are provided for controlling use of a register cache. The apparatus has execution circuitry for executing instructions to process data values, and a register file comprising a plurality of registers in which to store the data values for access by the execution circuitry. A register cache is also provided that has a plurality of entries and is arranged to cache a subset of the data values for access by the execution circuitry. Each entry is arranged to cache a data value and an indication of the register associated with that cached data value. Prefetch circuitry then performs prefetch operations to prefetch data values from the register file into the register cache. Timing indication storage is used to store, for each data value to be generated as a result of instructions being executed within the execution circuitry, a register identifier for that data value, and timing information indicating when that data value will be generated by the execution circuitry. Cache usage control circuitry is then responsive to receipt of a plurality of register identifiers associated with source data values for a pending instruction yet to be executed by the execution circuitry, to generate, with reference to the timing information in the timing indication storage, a timing control signal to control timing of at least one prefetch operation performed by the prefetch circuitry. Such an approach can lead to significant improvements in the efficiency of utilisation of the register cache.

公开(公告)号：US20190012177A1

公开(公告)日：2019-01-10

申请号：US16018492

申请日：2018-06-26

Applicant: ARM Limited

Inventor： Luca SCALABRINO ,  Frederic Jean Denis ARSANTO ,  Claire AUPETIT

IPC: G06F9/38 ,  G06F9/30

Abstract: An apparatus and method are provided for controlling use of a register cache. The apparatus has decode circuitry for decoding instructions retrieved from memory, execution circuitry to execute the decoded instructions in order to perform operations on data values, and a register file having a plurality of registers for storing the data values to be operated on by the execution circuitry. Further, a register cache is provided that comprises a plurality of entries, and is arranged to cache a subset of the data values. Each entry is arranged to cache a data value and an indication of the register associated with that cached data value. Prefetch circuitry is then used to prefetch data values from the register file into the register cache. Further, operand analysis circuitry derives source operand information for an instruction fetched from memory, at least prior to the decode circuitry completing decoding of that instruction. It then causes provision to the prefetch circuitry of at least one register identifier determined from the source operand information. The prefetch circuitry then utilises that at least one register identifier when determining which data values to prefetch into the register cache. Such an approach can significantly increase the hit rate within the register cache, hence improving performance.