公开(公告)号：US20210334643A1

公开(公告)日：2021-10-28

申请号：US16859062

申请日：2020-04-27

Applicant: Arm Limited

Inventor： Dominic Hugo SYMES ,  John Wakefield BROTHERS, III ,  Fredrik Peter STOLT

IPC: G06N3/08 ,  G06N3/04

Abstract: A processing unit is described that receives an instruction to perform a first operation on a first layer of a neural network, block dependency data, and an instruction to perform a second operation on a second layer of the neural network. The processing unit performs the first operation, which includes dividing the first layer into a plurality of input blocks, and operating on the input blocks to generate a plurality of output blocks. The processing unit then performs the second operation after the first operation has generated a set number of output blocks defined by the block dependency data.

公开(公告)号：US20230080578A1

公开(公告)日：2023-03-16

申请号：US17474619

申请日：2021-09-14

Applicant: Arm Limited

Inventor： Dominic Hugo SYMES ,  Fredrik Peter STOLT

IPC: G06F9/30 ,  G06N3/04

Abstract: A dot product array comprises dot product circuits each to process a respective pair of first and second input vectors to generate a respective dot product result. In a real number mode, each dot product result and vector element represents a respective real number. In a hypercomplex number mode, an input vector manipulation is applied to at least one of the first/second input vectors to be supplied to each dot product circuit, to cause the dot product array to generate hypercomplex dot product results each indicating a sum of hypercomplex products of corresponding pairs of hypercomplex numbers. In the hypercomplex number mode, respective subsets of elements of the first/second input vectors represent respective hypercomplex numbers, for which respective components are represented by different elements of the subset, and each hypercomplex dot product result comprises components represented by the dot product results generated by a corresponding group of at least two dot product circuits.

公开(公告)号：US20230259583A1

公开(公告)日：2023-08-17

申请号：US18167537

申请日：2023-02-10

Applicant: Arm Limited

Inventor： Fredrik Peter STOLT

IPC: G06F17/16 ,  G06F7/544

CPC classification number: G06F17/16 ,  G06F7/5443

Abstract: A method performed by a processing unit for generating an output feature map, the processing unit comprising an input feature map storage configured to store input feature map blocks. The input feature map storage is read by the processing unit to generate output feature map blocks. The method comprises sequentially loading input feature map blocks into the input feature map storage, using a first input feature map block stored in the input feature map storage to generate a partial computation for a first output feature map block, and reusing the first input feature map block stored in the input feature map storage to generate a partial computation for a second output feature map block without reloading the first input feature map block into the input feature map storage.

公开(公告)号：US20230367991A1

公开(公告)日：2023-11-16

申请号：US18312868

申请日：2023-05-05

Applicant: Arm Limited

Inventor： Anders Per SJÖ ,  Fredrik Peter STOLT ,  Stefan Johannes FRID

IPC: G06N3/02

CPC classification number: G06N3/02

Abstract: A method for generating output feature map data during operation of neural network processing by a processing unit comprising a plurality of computation resources. The method comprises obtaining first, real, data to be processed and loading the first data into a set of the plurality of computation resources, causing the set of computation resources to generate a computational result, in a first processing cycle of the processing unit. A lack of real data for processing in a second processing cycle of the processing unit, which is subsequent to the first processing cycle, is detected. The method comprises obtaining second, artificial, data, loading the second data into an artificially activated set, of the set of computation resources, in the second processing cycle, inhibiting the second data from affecting the output feature map data, and generating the output feature map data based at least in part on the computational result.

公开(公告)号：US20230367592A1

公开(公告)日：2023-11-16

申请号：US18312884

申请日：2023-05-05

Applicant: Arm Limited

Inventor： Peter Mattias HANSSON ,  Fredrik Peter STOLT

IPC: G06F9/30 ,  G06F9/345

CPC classification number: G06F9/3001 ,  G06F9/345

Abstract: A method comprising obtaining first, real, data to be processed. It is determined, based on a number of computation resources of a set of computation resources of a processing unit available for use during a processing cycle, to process at least a portion of the first data using a first subset of the set and to load second, artificial, data into a second subset of the set, disjoint from the first subset of the set, the second data comprising at least one artificial data element. In a processing cycle, at least the portion of the first data and the second data are loaded into first and second subsets of the set, respectively. The second subset is an artificially activated subset. The second data is inhibited from affecting output feature map data, which is generated based at least in part on the computational result.

公开(公告)号：US20230259332A1

公开(公告)日：2023-08-17

申请号：US18167196

申请日：2023-02-10

Applicant: Arm Limited

Inventor： Fredrik Peter STOLT

IPC: G06F7/544 ,  G06F7/57

CPC classification number: G06F7/5443 ,  G06F7/57

Abstract: A processing unit comprises a multiply-accumulate engine and a control unit. The engine comprises a plurality of dot product units, switching circuitry, a plurality of adders, and a plurality of accumulators. The switching circuitry, coupled between the dot product units and the adders, is configurable to selectively couple each of the adders to one of the plurality of dot product units. The adders are each associated with a respective accumulator of the plurality of accumulators. In a processing cycle, each of the dot product units is configured to output a product value, the control unit is operable to configure the switching circuitry such that each of the adders is coupled to a selected dot product unit of the plurality of dot product units, and each of the adders is configured to add the product value of the selected dot product unit to an accumulated value stored by the respective accumulator.