公开(公告)号：US11947962B2

公开(公告)日：2024-04-02

申请号：US16468098

申请日：2017-11-10

Applicant: ARM LIMITED

Inventor： Jacob Eapen ,  Grigorios Magklis ,  Mbou Eyole

IPC: G06F9/315 ,  G06F9/30

CPC classification number: G06F9/30032 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30109

Abstract: In response to a replicate partition instruction specifying partition information defining positions of a plurality of variable size partitions within a result vector, an instruction decoder (20) controls the processing circuitry (80) to generate a result vector in which each partition having more than one data element comprises data values or element indices of a sequence of data elements of a source vector starting or ending at a selected data element position. This instruction can be useful for accelerating processing of data structures smaller than the vector length.

公开(公告)号：US12061906B2

公开(公告)日：2024-08-13

申请号：US15745478

申请日：2016-06-15

Applicant: ARM LIMITED

Inventor： Nigel John Stephens ,  Jacob Eapen ,  Mbou Eyole

IPC: G06F9/315 ,  G06F9/30

CPC classification number: G06F9/30032 ,  G06F9/30018 ,  G06F9/30036

Abstract: An apparatus and a method are provided for performing a splice operation, the apparatus having a set of vector registers and one or more control registers. Processing circuitry is arranged to execute a sequence of instructions including a splice instruction that identifies at least a first vector register and at least one control register. The first vector register stores a first vector of data elements having a vector length, and the at least one control register stores control data identifying one or more data elements occupying sequential data element positions within the first vector of data elements. The processing circuitry is responsive to execution of the splice instruction to extract from the first vector each data element identified by the control data in the at least one control register, and to output the extracted data elements within sequential data element positions of the result vector starting from a first end of the result vector, and data elements from a second vector are output to the remaining result vector data element positions not occupied by the extracted data elements from the first vector.

公开(公告)号：US10678540B2

公开(公告)日：2020-06-09

申请号：US15973663

申请日：2018-05-08

Applicant: Arm Limited

Inventor： Jacob Eapen ,  Mbou Eyole ,  Neil Burgess

IPC: G06F9/30

Abstract: An apparatus and method are provided for efficiently performing arithmetic operations that include at least a multiplication operation. The apparatus comprises processing circuitry to perform data processing operations, and instruction decode circuitry responsive to program instructions to generate control signals to control the processing circuitry to perform the data processing operations. In response to an arithmetic operation with shift instruction specifying performance of an arithmetic operation comprising at least a multiplication operation, and having a field which provides a programmable shift indication, the instruction decode circuitry is configured to control the processing circuitry to perform the arithmetic operation during which an intermediate value is produced, and to select a target portion of the intermediate value based on an output window determined from the programmable shift indication.

公开(公告)号：US11977884B2

公开(公告)日：2024-05-07

申请号：US16468108

申请日：2017-11-10

Applicant: ARM LIMITED

Inventor： Jacob Eapen ,  Grigorios Magklis ,  Mbou Eyole

IPC: G06F9/315 ,  G06F9/30

CPC classification number: G06F9/30032 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30109

Abstract: A replicate elements instruction defining a plurality of variable length segments in a result vector controls processing circuitry (80) to generate a result vector in which, in each respective segment, a repeating value is repeated throughout that segment of the result vector, the repeating value comprising a data value or element index of a selected data element of a source vector. This instructions is useful for accelerating processing of data structures smaller than the vector length.

公开(公告)号：US11327752B2

公开(公告)日：2022-05-10

申请号：US16487256

申请日：2018-02-02

Applicant: ARM LIMITED

Inventor： Grigorios Magklis ,  Nigel John Stephens ,  Jacob Eapen ,  Mbou Eyole ,  David Hennah Mansell

IPC: G06F9/30 ,  G06F17/16 ,  G06F9/455

Abstract: A data processing apparatus, a method of operating a data processing apparatus, a non-transitory computer readable storage medium, and an instruction are provided. The instruction specifies a first source register, a second source register, and an index. In response to the instruction control signals are generated, causing processing circuitry to perform a data processing operation with respect to each data group in the first source register and the second source register to generate respective result data groups forming a result of the data processing operation. Each of the first source register and the second source register has a size which is an integer multiple at least twice a predefined size of the data group, and each data group comprises a plurality of data elements. The operands of the data processing operation for each data group are a selected data element identified in the data group of the first source register by the index and each data element in the data group of the second source register. A technique for element-by-vector operation which is readily scalable as the register width grows.

公开(公告)号：US11132196B2

公开(公告)日：2021-09-28

申请号：US16090357

申请日：2017-04-06

Applicant: ARM Limited

Inventor： Mbou Eyole ,  Jacob Eapen ,  Alejandro Martinez Vicente

IPC: G06F9/30 ,  G06F9/34 ,  G06F9/38

Abstract: Address collisions are managed when performing vector operations. A register store stores vector operands. Execution circuitry performs memory access operations to move the vector operands between the register store and memory and data processing operations using the vector operands. The execution circuitry may iteratively execute a vector loop, where during each iteration the execution circuitry executes a sequence of instructions to implement the vector loop. The sequence includes a check instruction identifying a plurality of memory addresses. The execution circuitry responds to the check instruction to determine whether an address hazard condition exists among the plurality of memory addresses. For each iteration of the vector loop, the execution circuitry responds to the check instruction determining an absence of the hazard address condition to employ a default level of vectorization when executing the sequence of instructions to implement the vector loop. But in the presence of the address hazard condition, the execution circuitry employs a reduced level of vectorization to implement the vector loop.

公开(公告)号：US12259821B2

公开(公告)日：2025-03-25

申请号：US17310368

申请日：2020-01-29

Applicant: ARM LIMITED

Inventor： Simon John Craske ,  Jacob Eapen

IPC: G06F12/10 ,  G06F12/14

Abstract: There is provided an apparatus comprising input circuitry that receives requests comprising input addresses in an input domain. Output circuitry provides output addresses. The output addresses comprise secure physical addresses to secure storage circuitry and non-secure physical addresses to non-secure storage circuitry. Lookup circuitry stores a plurality of mappings comprising at least one mapping between the input addresses and the secure physical addresses, and at least one mapping between the input addresses and the non-secure physical addresses.

公开(公告)号：US11086715B2

公开(公告)日：2021-08-10

申请号：US16251503

申请日：2019-01-18

Applicant: Arm Limited

Inventor： Matthias Lothar Boettcher ,  François Christopher Jacques Botman ,  Jacob Eapen

IPC: G06F11/10 ,  G06F11/14

Abstract: An apparatus comprising data processing circuitry for processing data in one of a plurality of operating states, an instruction decoder for decoding instructions and error checking circuitry for performing error checking operations. In response to a touch instruction being decoded by the instruction decoder, error checking operation is performed on selected architectural state. The architectural state is architecturally inaccessible to the operating state. As a result of the touch instruction, the architectural state remains unchanged, at least when no error is detected.

公开(公告)号：US09965275B2

公开(公告)日：2018-05-08

申请号：US14814582

申请日：2015-07-31

Applicant: ARM LIMITED

Inventor： Jacob Eapen ,  Mbou Eyole ,  Simon Hosie

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032

Abstract: An apparatus comprises processing circuitry to generate a result vector including at least one N-bit data element in response to an element size increasing instruction identifying at least a first input vector including M-bit data elements, where N>M. First and second forms of the element size increasing instruction are provided for generating the result vector using first and second subsets of data elements of the first input vector respectively. Positions of the first and second subsets of data elements in the first input vector are interleaved.