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    Comparing a runlength of bits with a variable number
    1.
    发明授权
    Comparing a runlength of bits with a variable number 有权

    公开(公告)号：US10534580B2

    公开(公告)日：2020-01-14

    申请号：US14606217

    申请日：2015-01-27

    Applicant: ARM LIMITED

    Inventor： Neil Burgess ,  David Raymond Lutz

    IPC: G06F7/74

    Abstract: Processing circuitry is provided for comparing a number of adjacent widths having a common value and extending from a starting position within an input number with a runlength specified by a variable number. The circuitry includes a mask generator for generating a mask value in dependence upon the variable number, combination circuitry for performing a logical combination operation upon respective bits within the input number starting from the starting position and corresponding bits within the mask value so as to generate an intermediate value. Result circuitry then generates a result indicative of whether or not the number of adjacent bits is less than or equal to the run length in dependence upon a determination if any bits within the intermediate value have a predetermined value.

    Encoding special value in anchored-data element
    2.
    发明授权
    Encoding special value in anchored-data element 有权

    公开(公告)号：US10459688B1

    公开(公告)日：2019-10-29

    申请号：US16268665

    申请日：2019-02-06

    Applicant: Arm Limited

    Inventor： Neil Burgess ,  Christopher Neal Hinds ,  David Raymond Lutz

    IPC: G06F7/485 ,  G06F7/487

    Abstract: An apparatus comprises: processing circuitry to perform data processing; and an instruction decoder to control the processing circuitry to perform an anchored-data processing operation to generate an anchored-data element. The anchored-data element has an encoding including type information indicative of whether the anchored-data element represents: a portion of bits of a two's complement number, said portion of bits corresponding to a given range of significance representable using the anchored-data element; or a special value other than said portion of bits of a two's complement number.

    Overlap propagation operation
    3.
    发明授权
    Overlap propagation operation 有权

    公开(公告)号：US09928031B2

    公开(公告)日：2018-03-27

    申请号：US14939301

    申请日：2015-11-12

    Applicant: ARM LIMITED

    Inventor： Neil Burgess ,  David Raymond Lutz ,  Christopher Neal Hinds

    IPC: G06F7/483 ,  G06F7/50

    CPC classification number: G06F7/483 ,  G06F7/50 ,  G06F2207/4924

    Abstract: Processing circuitry is provided to perform an overlap propagating operation on a first data value to generate a second data value, the first and second data values having a redundant representation representing a P-bit numeric value using an M-bit data value comprising a plurality of N-bit portions, where M>P>N. In the redundant representation, each N-bit portion other than a most significant N-bit portion includes a plurality of overlap bits having a same significance as a plurality of least significant bits of a following N-bit portion. Each N-bit portion of the second data value other than a least significant N-bit portion is generated by adding non-overlap bits of a corresponding N-bit portion of the first data value to the overlap bits of a preceding N-bit portion of the first data value. This provides a faster technique for reducing the chance of overflow during addition of the redundantly represented M-bit value.

    Standalone floating-point conversion unit
    5.
    发明授权
    Standalone floating-point conversion unit 有权
    独立浮点转换单元

    公开(公告)号：US09582248B2

    公开(公告)日：2017-02-28

    申请号：US14498172

    申请日：2014-09-26

    Applicant: ARM Limited

    Inventor： David Raymond Lutz ,  Neil Burgess

    IPC: G06F5/01 ,  G06F7/485

    CPC classification number: G06F7/485

    Abstract: A data processing apparatus includes floating-point adder circuitry and floating-point conversion circuitry that generates a floating-point number as an output by performing a conversion on any input having a format from a list of formats including: an integer number, a fixed-point number, and a floating-point number having a format smaller than the output floating-point number. The floating-point conversion circuitry is physically distinct from the floating-point adder circuitry.

    Abstract translation: 数据处理装置包括浮点加法器电路和浮点转换电路，其通过对从格式列表格式的任何输入执行转换来产生浮点数，该格式包括：整数， 点数，以及格式小于输出浮点数的浮点数。 浮点转换电路在物理上不同于浮点加法器电路。

    Predicting saturation in a shift operation
    6.
    发明授权
    Predicting saturation in a shift operation 有权
    预测换档操作中的饱和度

    公开(公告)号：US09564187B2

    公开(公告)日：2017-02-07

    申请号：US14933402

    申请日：2015-11-05

    Applicant: ARM Limited

    Inventor： David Raymond Lutz ,  Neil Burgess

    IPC: G11C7/00 ,  G11C7/10 ,  G06F5/01 ,  G06F9/30 ,  G06F7/499

    CPC classification number: G11C7/1078 ,  G06F5/01 ,  G06F7/49921 ,  G06F9/30018 ,  G06F9/30032 ,  G11C7/1084

    Abstract: Apparatus for data processing and a method of data processing are provided. Shift circuitry performs a shift operation in response to a shift instruction, shifting bits of an input data value in a direction specified by the shift instruction. Bit location indicator generation circuitry and comparison circuitry operate in parallel with the shift circuitry. The bit location indicator indicates at least one bit location in the input data value which must not have a bit set if the shifted data value is not to saturate. Comparison circuitry compares the bit location indicator with the input data value and indicates a saturation condition if any bits are indicated by the bit position indicator for bit locations which hold set bits in the input data value. A faster indication of the saturation condition thus results.

    Abstract translation: 提供了数据处理装置和数据处理方法。 移位电路响应于移位指令执行移位操作，在由移位指令指定的方向上移位输入数据值的位。 位位置指示符生成电路和比较电路与移位电路并行操作。 位位置指示符指示输入数据值中的至少一个位位置，如果移位的数据值不饱和，则该位置不能有位置位。 比较电路将位位置指示符与输入数据值进行比较，并且如果位位置指示符指示了用于保持输入数据值中的设置位的位位置的任何位，则表示饱和条件。 因此，更快地显示饱和条件。

    FLOATING-POINT NUMBER DECODER
    7.
    发明公开
    FLOATING-POINT NUMBER DECODER 审中-公开

    公开(公告)号：US20240036821A1

    公开(公告)日：2024-02-01

    申请号：US18199151

    申请日：2023-05-18

    Applicant: Arm Limited

    Inventor： Neil Burgess ,  Sangwon Ha ,  Partha Prasun Maji

    IPC: G06F7/483

    CPC classification number: G06F7/483

    Abstract: In a data processor, an input datum, having a sign, a tag and a payload, is decoded by first determining a format of the payload based on the tag. For a first format, an exponent difference and an output fraction are decoded from the payload. For a second format, an exponent difference is decoded from the payload and the output fraction may be assumed to be zero. The exponent difference is subtracted from a shared exponent to produce the output exponent. The decoded output may be stored in a standard format for floating-point numbers.

    HIGH-PRECISION ANCHORED-IMPLICIT PROCESSING
    8.
    发明申请
    HIGH-PRECISION ANCHORED-IMPLICIT PROCESSING 有权

    公开(公告)号：US20220129245A1

    公开(公告)日：2022-04-28

    申请号：US17081068

    申请日：2020-10-27

    Applicant: Arm Limited

    Inventor： Neil Burgess ,  Christopher Neal Hinds ,  David Raymond Lutz ,  Pedro Olsen Ferreira

    IPC: G06F7/499 ,  G06F7/487 ,  G06F9/38

    Abstract: An apparatus includes a processing circuit and a storage device. The processing circuit is configured to perform one or more processing operations in response to one or more instructions to generate an anchored-data element. The storage device is configured to store the anchored-data element. A format of the anchored-data element includes an identification item, an overlap item, and a data item. The data item is configured to hold a data value of the anchored-data element. The identification item indicates an anchor value for the data value or one or more special values.

    Multiplier circuit
    9.
    发明授权
    Multiplier circuit 有权

    公开(公告)号：US11068238B2

    公开(公告)日：2021-07-20

    申请号：US16417866

    申请日：2019-05-21

    Applicant: Arm Limited

    Inventor： Michael Alexander Kennedy ,  Neil Burgess ,  Zichao Xie ,  Chiloda Ashan Senarath Pathirane

    IPC: G06F7/53 ,  G06F7/509

    Abstract: A multiplier circuit is described in which sub-products calculated in a first stage of a carry-save adder (CSA) network are output early, processed by applying a processing function, and re-injected into a subsequent stage of the CSA network to add the processed sub-products. This allows a CSA network provided for multiplication operations to be reused for operations which require sub-products to be processed and added, such as floating-point dot product operations performed on floating-point values represented in bfloatl6 format.

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