SECURE MEMORY TRANSLATIONS
    1.
    发明申请

    公开(公告)号:US20210240629A1

    公开(公告)日:2021-08-05

    申请号:US16782316

    申请日:2020-02-05

    Applicant: Arm Limited

    Abstract: An apparatus is provided, connectable to a memory and one or more peripherals. The apparatus includes translation request circuitry to receive a translation request from one of the peripherals to translate an input address within an input domain to an output address within an output domain. Signing circuitry generates a signature of at least part of the output address using a private key. Translation response circuitry responds to the translation request by transmitting to the one of the peripherals a translation response, including the output address and the signature. Gateway circuitry receives access requests to the memory. Each of the access requests comprises a desired memory address in the output domain and a signature of the desired memory address. The gateway performs validation of the signature of the desired memory address using the private key and in response to the validation of a given access request failing, performs an error action.

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