公开(公告)号：US20240256436A1

公开(公告)日：2024-08-01

申请号：US18162491

申请日：2023-01-31

Applicant: Arm Limited

Inventor： Kévin Petit

IPC: G06F12/02 ,  G06F9/48

CPC classification number: G06F12/023 ,  G06F9/4881 ,  G06F2212/251

Abstract: A system, method and computer program product configured to control a plurality of parallel programs operating in an n-dimensional hierarchical iteration space over an n-dimensional data space, comprising: a processor and a memory configured to accommodate the plurality of parallel programs and the data space; a memory access control decoder configured to decode memory location references to regions of the n-dimensional data space from indices in the plurality of parallel programs; and an execution orchestrator responsive to the memory access control decoder and configured to sequence regions of the n-dimensional hierarchical iteration space of the plurality of parallel programs to honour a data requirement of at least a first of the plurality of parallel programs having a data dependency on at least a second of the plurality of parallel programs.

公开(公告)号：US12182011B2

公开(公告)日：2024-12-31

申请号：US18162491

申请日：2023-01-31

Applicant: Arm Limited

Inventor： Kévin Petit

IPC: G06F12/02 ,  G06F9/48

Abstract: A system, method and computer program product configured to control a plurality of parallel programs operating in an n-dimensional hierarchical iteration space over an n-dimensional data space, comprising: a processor and a memory configured to accommodate the plurality of parallel programs and the data space; a memory access control decoder configured to decode memory location references to regions of the n-dimensional data space from indices in the plurality of parallel programs; and an execution orchestrator responsive to the memory access control decoder and configured to sequence regions of the n-dimensional hierarchical iteration space of the plurality of parallel programs to honour a data requirement of at least a first of the plurality of parallel programs having a data dependency on at least a second of the plurality of parallel programs.

公开(公告)号：US20240394061A1

公开(公告)日：2024-11-28

申请号：US18660683

申请日：2024-05-10

Applicant: Arm Limited

Inventor： John David Robson ,  Kévin Petit

IPC: G06F9/30

Abstract: Disclosed is an apparatus comprising: instruction decoding circuitry; data storage; and processing circuitry to process data responsive to an instruction decoded by instruction decoding circuitry configured to, responsive to a data transfer instruction specifying a data source and a region of the source to perform data transfer, control processing circuitry to: when the data transfer operation comprises an out-of-bounds memory access corresponding to an attempt to read data outside the indicated region of source storage, read data not associated with the out-of-bounds memory access from source storage and write data not associated with the out-of-bounds memory access to a first portion of target storage by overwriting preloaded values stored in the first portion of the target storage; and omit writing to a different second portion of the target storage data associated with the out-of-bounds memory access to preserve preloaded values stored in the second portion of target storage.