公开(公告)号：US11276137B1

公开(公告)日：2022-03-15

申请号：US17201229

申请日：2021-03-15

Applicant: Arm Limited

Inventor： Isidoros Sideris ,  Stephane Forey ,  William Robert Stoye ,  John David Robson

IPC: G06T1/20 ,  G06T1/60

Abstract: There is provided a graphics processor comprising a programmable execution unit operable to execute programs for respective execution thread groups. An eviction checking circuit is provided that is configured to check instructions as they are being fetched for execution from an instruction cache to determine whether the instruction includes any conditional eviction conditions that if not met indicate that the program to which the instruction relates should not continue to be executed for the group of execution threads. The eviction checking circuit is then configured to check whether any conditional eviction conditions are satisfied at this point and either allow the execution unit to continue program execution or cause the thread group to be evicted.

公开(公告)号：US11442731B2

公开(公告)日：2022-09-13

申请号：US16656385

申请日：2019-10-17

Applicant: Arm Limited

Inventor： John David Robson ,  Sean Tristram LeGuay Ellis ,  William Robert Stoye

IPC: G06F9/30

Abstract: A data processor includes an execution unit that executes instructions to perform data processing operations, a register file operable to store data values for use by and produced by the execution unit, and a buffer intermediate between the register file for providing data values from the register file to the execution unit for use when executing an instruction, and to receive output data values from the execution unit for writing to the register file.
Instructions to be executed by the execution unit of the data processor have associated buffer eviction priority indications representative of a priority for eviction from the buffer of an output data value that will be generated when executing the instruction. The buffer eviction priority indications are then used when selecting data values to evict from the buffer.

公开(公告)号：US20210117192A1

公开(公告)日：2021-04-22

申请号：US16656385

申请日：2019-10-17

Applicant: Arm Limited

Inventor： John David Robson ,  Sean Tristram LeGuay Ellis ,  William Robert Stoye

IPC: G06F9/30

Abstract: A data processor includes an execution unit that executes instructions to perform data processing operations, a register file operable to store data values for use by and produced by the execution unit, and a buffer intermediate between the register file for providing data values from the register file to the execution unit for use when executing an instruction, and to receive output data values from the execution unit for writing to the register file.
Instructions to be executed by the execution unit of the data processor have associated buffer eviction priority indications representative of a priority for eviction from the buffer of an output data value that will be generated when executing the instruction. The buffer eviction priority indications are then used when selecting data values to evict from the buffer.

公开(公告)号：US20240394061A1

公开(公告)日：2024-11-28

申请号：US18660683

申请日：2024-05-10

Applicant: Arm Limited

Inventor： John David Robson ,  Kévin Petit

IPC: G06F9/30

Abstract: Disclosed is an apparatus comprising: instruction decoding circuitry; data storage; and processing circuitry to process data responsive to an instruction decoded by instruction decoding circuitry configured to, responsive to a data transfer instruction specifying a data source and a region of the source to perform data transfer, control processing circuitry to: when the data transfer operation comprises an out-of-bounds memory access corresponding to an attempt to read data outside the indicated region of source storage, read data not associated with the out-of-bounds memory access from source storage and write data not associated with the out-of-bounds memory access to a first portion of target storage by overwriting preloaded values stored in the first portion of the target storage; and omit writing to a different second portion of the target storage data associated with the out-of-bounds memory access to preserve preloaded values stored in the second portion of target storage.

公开(公告)号：US20250138827A1

公开(公告)日：2025-05-01

申请号：US18927890

申请日：2024-10-26

Applicant: Arm Limited

Inventor： John David Robson ,  Edvard Fielding ,  Kalyani Rajkumar ,  Philip Michael Watts

IPC: G06F9/30

Abstract: A computer implemented method for processing instructions in a multiprocessing apparatus comprises obtaining a first instruction of a first process; decoding the first instruction to detect a continuation indicator associated with the first instruction; determining whether or not to enforce the continuation indicator; and when it is determined to enforce the continuation indicator: continuing to execute the first process until completion of the first instruction and at least a next sequential second instruction of the first process. The continuation may temporarily suppress a normal eviction process based on a fairness algorithm, for example.