公开(公告)号：US20230124622A1

公开(公告)日：2023-04-20

申请号：US17501642

申请日：2021-10-14

Applicant: Arm Limited

Inventor： Shashank Guruprasad ,  Roma Rudra ,  Mikael Yves Marie Rien ,  Karthik Sankaranarayanan

IPC: H03K3/027 ,  H03K3/023 ,  H03K5/00 ,  H03K19/21

Abstract: According to one implementation of the present disclosure, a circuit includes: two or more metal wires, respective XOR gates coupled to each of the two or more top metal wires, a shift register having outputs coupled to the XOR gates, an OR gate configured to receive each of the outputs of the XOR gates, and a latch configured to receive an output of the OR gate and transmit an output signal corresponding to an alarm signal.

公开(公告)号：US20230077386A1

公开(公告)日：2023-03-16

申请号：US17472556

申请日：2021-09-10

Applicant: Arm Limited

Inventor： Shashank Guruprasad ,  Roma Rudra ,  Karthik Sankaranarayanan ,  Mikael Yves Marie Rien

IPC: G06F21/76 ,  G06F9/30

Abstract: Various implementations described herein refer to a device having base registers that receive input signals, receive a reset signal and provide first output signals based on the input signals and the reset signal. The device may have shadow registers that correspond to the base registers, wherein the shadow registers receive inverted input signals, receive an inverted reset signal and provide second output signals based on the inverted input signals and the inverted reset signal. The device may have attack detector logic that receives the first output signals from the base registers, receives the second output signals from the shadow registers and generates an alarm signal based on the first output signals and the second output signals.

公开(公告)号：US12176904B2

公开(公告)日：2024-12-24

申请号：US17501642

申请日：2021-10-14

Applicant: Arm Limited

Inventor： Shashank Guruprasad ,  Roma Rudra ,  Mikael Yves Marie Rien ,  Karthik Sankaranarayanan

IPC: H03K3/027 ,  G06F21/75 ,  G06F21/86 ,  H03K3/023 ,  H03K5/00 ,  H03K19/21

Abstract: According to one implementation of the present disclosure, a circuit includes: two or more metal wires, respective XOR gates coupled to each of the two or more top metal wires, a shift register having outputs coupled to the XOR gates, an OR gate configured to receive each of the outputs of the XOR gates, and a latch configured to receive an output of the OR gate and transmit an output signal corresponding to an alarm signal.