公开(公告)号：US20220066840A1

公开(公告)日：2022-03-03

申请号：US17446796

申请日：2021-09-02

Applicant: Arm Limited

Inventor： Mark Salling RUTLAND ,  Gareth Rhys STOCKWELL ,  Christoffer DALL ,  Jade Ella Carla ALGLAVE

IPC: G06F9/52 ,  G06F9/48

Abstract: Apparatus comprises a data memory to store lock data for each of a set of processing resources, the lock data representing lock status data and tag data indicating a resource type selected from a plurality of resource types; and a processing element to execute an atomic operation with respect to the lock data for a given processing resource, the atomic operation comprising at least: a detection of whether the given processing resource is of a required resource type; a detection from the lock status data whether the given processing resource is currently unlocked; and when the given processing resource is detected to be currently unlocked and of the required resource type, performance of a predetermined action with respect to one or both of the lock status data and the tag data.

公开(公告)号：US20230214224A1

公开(公告)日：2023-07-06

申请号：US17998299

申请日：2021-05-13

Applicant: Arm Limited

Inventor： John Michael HORLEY ,  Michael John WILLIAMS ,  Mark Salling RUTLAND ,  Alasdair GRANT

IPC: G06F9/38

CPC classification number: G06F9/3865 ,  G06F9/3867

Abstract: A technique for collecting state information of an apparatus comprising a processing pipeline for executing a sequence of instructions, and interesting instruction designation circuitry for identifying at least one of the instructions in the sequence as being an interesting instruction. Each interesting instruction is an instruction for which given state information of the apparatus associated with execution of that interesting instruction is to be collected. The interesting instruction designation circuitry is arranged, for each identified interesting instruction, to apply defined selection criteria to determine a further instruction later in the sequence of instructions than the interesting instruction, and to mark that further instruction as having a synchronous exception associated therewith. The processing pipeline is responsive to the further instruction, which causes the processing pipeline to execute a given exception handling routine in order to collect the given state information.

公开(公告)号：US20230342303A1

公开(公告)日：2023-10-26

申请号：US17998744

申请日：2021-05-14

Applicant: ARM LIMITED

Inventor： Richard Roy GRISENTHWAITE ,  Jason PARKER ,  Mark Salling RUTLAND ,  Yuval ELAD

IPC: G06F12/1045 ,  G06F12/14

CPC classification number: G06F12/1045 ,  G06F12/14 ,  G06F2212/1052

Abstract: An apparatus has address translation circuitry to translate a target virtual address (VA) specified by a memory access request into a target physical address, first/second translation table address storage circuitry to store first/second translation table addresses; and protected region defining data storage circuitry to store region defining data specifying at least one protected region of virtual address space. In response to the memory access request: when the target VA is in the protected region(s), the address translation circuitry translates the target VA based on address translation data from a first translation table structure identified by the first translation table address. When the target VA is outside the protected region(s), the target VA is translated based on address translation data from a second translation table structure identified by the second translation table address.