公开(公告)号：US12079379B2

公开(公告)日：2024-09-03

申请号：US17111007

申请日：2020-12-03

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Denis Remezov ,  Yin Tan ,  Jingshun Chen

IPC: G06F21/85 ,  G06F12/10 ,  G06F12/14 ,  G06F13/28 ,  G06F13/40 ,  G06F13/42 ,  G06F21/44

CPC classification number: G06F21/85 ,  G06F12/10 ,  G06F12/14 ,  G06F13/28 ,  G06F13/4027 ,  G06F13/4282 ,  G06F21/44 ,  G06F2212/1052 ,  G06F2213/0026

Abstract: The disclosed systems, structures, and methods are directed to a computer system including a PCIe protection controller as a part of a PCIe root complex that includes at least one root port. Each root port is configured to optionally connect to at least one endpoint device, and each endpoint device is designated as a secure endpoint device or a nonsecure endpoint device. The PCIe protection controller is configured to control outbound traffic to protect secure endpoint devices from access from any nonsecure components of the computer system. The PCIe protection controller may be further configured to control inbound traffic to prevent access to secure memory by nonsecure endpoint devices. The PCIe protection controller may be dynamically configured at runtime to designate endpoint devices as either secure or nonsecure.

公开(公告)号：US20240211597A1

公开(公告)日：2024-06-27

申请号：US18089474

申请日：2022-12-27

Applicant: Sophos Limited

Inventor： Mark Willem LOMAN ,  Lute Wdwin ENGELS ,  Ronny Henk Gert TIJINK ,  Alexander VERMANING

IPC: G06F21/56 ,  G06F12/14

CPC classification number: G06F21/566 ,  G06F12/14 ,  G06F21/564

Abstract: Embodiments disclosed herein include an apparatus with a processor configured to receive an indication of a function call to an identified shared library and configured to perform an identified function. The processor is configured to insert a function hook in the shared library. The function hook is configured to pause the execution of the shared library when called. In response to the function hook, the processor is configured to identify a source location in one or more memories associated with an origin of the function call to the shared library. The processor is configured to scan a range of memory addresses associated with the source location in the one or more memories, and identify, based on the scanning, a potentially malicious process within the range of memory addresses.

公开(公告)号：US11914522B2

公开(公告)日：2024-02-27

申请号：US17907206

申请日：2021-02-08

Applicant: ARM LIMITED

Inventor： Jason Parker

IPC: G06F12/10 ,  G06F12/1027 ,  G06F12/14

CPC classification number: G06F12/10 ,  G06F12/1027 ,  G06F12/14 ,  G06F2212/1032

Abstract: Apparatuses, methods, and programs for performing a translation of a virtual address of a memory access to a physical address associated with a memory location to be accessed are disclosed. A page table descriptor is accessed when performing the translation, which comprises translation parameters for the translation. The descriptor further comprises an integrity check value, wherein the integrity check value is dependent on the translation parameters.

公开(公告)号：US11868233B2

公开(公告)日：2024-01-09

申请号：US17983624

申请日：2022-11-09

Applicant: GE Aviation Systems LLC

Inventor： Joachim Karl Ulf Hochwarth ,  Terrell Michael Brace ,  Víctor Mario Leal Herrera ,  Antonio Lugo Trejo

IPC: G06F11/36 ,  G06F12/14 ,  G06F21/62 ,  G09B9/08 ,  G06F8/65

CPC classification number: G06F11/3612 ,  G06F12/14 ,  G06F12/1458 ,  G06F21/62 ,  G09B9/08 ,  G06F8/65 ,  G06F2212/1052

Abstract: A system for read-access of a regulated system, the system comprising a specialized data store, at least one memory, and a flexible reader. The specialized data store able to receive at least a portion of a set of procedures that define a respective set of systematic data and executable operations. The at least one memory including at least one set of data related to the set of procedures.

公开(公告)号：US20230412365A1

公开(公告)日：2023-12-21

申请号：US18241748

申请日：2023-09-01

Applicant: Intel Corporation

Inventor： Thomas E. Willis ,  Brad Burres ,  Amit Kumar

IPC: H04L9/08 ,  G06F3/06 ,  G06F9/50 ,  H04L69/12 ,  H04L69/32 ,  G06F16/25 ,  G06F16/2453 ,  H04L49/9005 ,  G11C8/12 ,  G11C29/02 ,  H04L41/0896 ,  G06F30/34 ,  B25J15/00 ,  G06F1/18 ,  G06F1/20 ,  G06F11/34 ,  G06F15/78 ,  H04L41/5025 ,  H04L67/1008 ,  H05K7/14 ,  H05K7/18 ,  H05K7/20 ,  H04L67/1001 ,  G11C29/36 ,  G11C29/38 ,  G11C29/44 ,  G06F16/22 ,  G06F16/2455 ,  G06F12/02 ,  G06F12/14 ,  G06F13/16 ,  G06F15/173 ,  G06F13/40 ,  G06F13/42 ,  G06F9/448 ,  G06F9/28 ,  G06F15/16 ,  H04L41/0893 ,  H04L69/22 ,  H04L69/321 ,  H04L41/0213 ,  H04L41/0668 ,  H04L41/0677 ,  H04L45/28 ,  H04L45/7453 ,  H04L47/11 ,  H04L47/125 ,  H04L49/00 ,  H04L49/351 ,  G06F9/4401 ,  G06F9/445 ,  G06F12/06 ,  G06F16/23 ,  G06F16/248 ,  G06F16/901 ,  G06F16/11

CPC classification number: H04L9/0819 ,  G06F3/0631 ,  G06F3/067 ,  G06F3/0659 ,  G06F3/0604 ,  G06F9/5044 ,  H04L69/12 ,  H04L69/32 ,  G06F16/25 ,  G06F16/2453 ,  G06F9/5088 ,  H04L49/9005 ,  G11C8/12 ,  G11C29/028 ,  H04L41/0896 ,  G06F3/0605 ,  G06F30/34 ,  B25J15/0014 ,  G06F1/183 ,  G06F1/20 ,  G06F9/505 ,  G06F11/3442 ,  G06F15/7807 ,  G06F15/7867 ,  H04L41/5025 ,  H04L67/1008 ,  H05K7/1489 ,  H05K7/18 ,  H05K7/20209 ,  H05K7/20736 ,  H04L67/1001 ,  G11C29/36 ,  G11C29/38 ,  G11C29/44 ,  G06F16/221 ,  G06F16/2237 ,  G06F16/24553 ,  G06F16/2282 ,  G06F12/023 ,  G06F12/14 ,  G06F13/1663 ,  G06F15/17331 ,  G06F3/0611 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/42 ,  G06F3/0613 ,  G06F3/0629 ,  G06F9/4494 ,  G06F9/28 ,  G06F15/161 ,  G06F3/0644 ,  G06F3/0683 ,  H04L41/0893 ,  H04L69/22 ,  H04L69/321 ,  H04L41/0213 ,  H04L41/0668 ,  H04L41/0677 ,  H04L45/28 ,  H04L45/7453 ,  H04L47/11 ,  H04L47/125 ,  H04L49/30 ,  H04L49/351 ,  G06F9/4406 ,  G06F9/4411 ,  G06F9/445 ,  G06F3/0632 ,  G06F3/065 ,  G06F3/0685 ,  G06F3/0673 ,  G06F12/0607 ,  G06F16/2455 ,  G06F16/2365 ,  G06F16/248 ,  G06F16/2255 ,  G06F16/9014 ,  G06F16/119 ,  G06F3/0647 ,  G06F12/06 ,  H04L9/0894 ,  G06F2209/509 ,  G06F9/4401 ,  G06F9/44

Abstract: Technologies for processing network packets by a host interface of a network interface controller (NIC) of a compute device. The host interface is configured to retrieve, by a symmetric multi-purpose (SMP) array of the host interface, a message from a message queue of the host interface and process, by a processor core of a plurality of processor cores of the SMP array, the message to identify a long-latency operation to be performed on at least a portion of a network packet associated with the message. The host interface is further configured to generate another message which includes an indication of the identified long-latency operation and a next step to be performed upon completion. Additionally, the host interface is configured to transmit the other message to a corresponding hardware unit scheduler as a function of the subsequent long-latency operation to be performed. Other embodiments are described herein.

公开(公告)号：US11783060B2

公开(公告)日：2023-10-10

申请号：US16479714

申请日：2018-01-24

Applicant: The Trustees of Princeton University

Inventor： Niraj K. Jha

IPC: G06F21/60 ,  H04W12/03 ,  H04W12/42 ,  H04W12/106 ,  G06N20/10 ,  G06N3/04 ,  G06N3/08 ,  H04L9/32 ,  H04L69/04 ,  H04W4/38 ,  G06F12/14 ,  H04W84/18

CPC classification number: G06F21/606 ,  G06F12/14 ,  G06N3/04 ,  G06N3/08 ,  G06N20/10 ,  H04L9/3239 ,  H04L69/04 ,  H04W4/38 ,  H04W12/03 ,  H04W12/106 ,  H04W12/42 ,  H04W84/18 ,  H04L2209/72 ,  Y02D30/70

Abstract: Devices and methods for processing detected signals at a detector using a processor are provided. The system involves (i) a data compressor that implements an algorithm for converting a set of data into a compressed set of data, (ii) a machine learning (ML) module coupled to the data compressor, the ML module transforming the compressed set of data into a vector and filtering the vector, (iii) a data encryptor coupled to the ML module that encrypts the filtered vector, and (iv) an integrity protection module coupled to the ML module, wherein the integrity protection module protects the integrity of the filtered vector.

公开(公告)号：US11743692B2

公开(公告)日：2023-08-29

申请号：US16946450

申请日：2020-06-22

Applicant: Intrepid Networks, LLC

Inventor： Brittin Kane ,  Joseph Daniel McCall ,  Joshua Witter ,  Jason Alan Stonebraker

IPC: H04W4/08 ,  G06Q50/26 ,  G06Q10/10 ,  G06F15/167 ,  H04L67/1097 ,  G06F21/62 ,  G06F9/445 ,  G06F3/041 ,  G06F21/31 ,  G06F21/64 ,  G06Q10/063 ,  H04W24/08 ,  G06F3/0488 ,  G06F3/04817 ,  G06F16/955 ,  G06F21/60 ,  G06F3/06 ,  G06F21/55 ,  G06F12/14 ,  H04L67/01 ,  H04L9/40 ,  G06F3/0482 ,  H04L41/22

CPC classification number: H04W4/08 ,  G06F3/041 ,  G06F3/0488 ,  G06F3/04817 ,  G06F3/062 ,  G06F9/445 ,  G06F12/14 ,  G06F15/167 ,  G06F16/9554 ,  G06F21/31 ,  G06F21/556 ,  G06F21/604 ,  G06F21/62 ,  G06F21/629 ,  G06F21/6218 ,  G06F21/64 ,  G06Q10/063 ,  G06Q10/10 ,  G06Q50/26 ,  G06Q50/265 ,  H04L63/10 ,  H04L63/302 ,  H04L67/01 ,  H04L67/1097 ,  H04W24/08 ,  G06F3/0482 ,  G06F2203/04104 ,  G06F2221/2143 ,  H04L41/22

Abstract: A system which comprises a series of native applications, suited to run on mobile devices, and a series of web-based applications for which functionality and processing are optimized. The native applications and the web-based applications are coordinated to optimize processes of acquiring, storing and disseminating data for speed, integrity and security.

公开(公告)号：US11733972B2

公开(公告)日：2023-08-22

申请号：US17064540

申请日：2020-10-06

Applicant: Ventana Micro Systems Inc.

Inventor： John G. Favor ,  Srivatsan Srinivasan

IPC: G06F21/55 ,  G06F12/14 ,  G06F7/58 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F7/584 ,  G06F7/588 ,  G06F9/30101 ,  G06F9/3836 ,  G06F12/14 ,  G06F21/556 ,  G06F2207/581 ,  G06F2207/583

Abstract: A microprocessor that mitigates side channel attacks. The microprocessor includes a data cache memory and a load unit that receive a load operation that specifies a load address. The processor performs speculative execution of instructions and executes instructions out of program order. The load unit detects that the load operation does not have permission to access the load address or that the load address specifies a location for which a valid address translation does not currently exist and provides random load data as a result of the execution of the load operation.

公开(公告)号：US20190232891A1

公开(公告)日：2019-08-01

申请号：US16338616

申请日：2017-10-24

Applicant: Hitachi Automotive Systems, Ltd.

Inventor： Tasuku ISHIGOOKA ,  Tomohito EBINA ,  Kazuyoshi SERIZAWA

IPC: B60R16/02 ,  G06F12/14

CPC classification number: B60R16/02 ,  G06F12/14 ,  G06F2212/1052

Abstract: The present invention provides a vehicle control device capable of realizing access authority definitions by the number equal to or greater than the number of access control registers provided in a memory protection device. In the vehicle control device according to the present invention, the whole or a part of a storage device that stores the access authority definitions used by the memory protection device to control the access authorities, is allocated fixedly to a memory area in advance and the rest is allocated dynamically.

公开(公告)号：US20190220196A1

公开(公告)日：2019-07-18

申请号：US16360115

申请日：2019-03-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa

IPC: G06F3/06 ,  G06F12/06 ,  G06F13/16 ,  G06F12/14

CPC classification number: G06F3/0604 ,  G06F3/0611 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/06 ,  G06F12/0623 ,  G06F12/14 ,  G06F13/1657 ,  G06F13/1694 ,  G06F2212/1024 ,  G06F2212/1028 ,  G06F2212/1052 ,  G06F2212/214 ,  G06F2212/2532 ,  Y02D10/14

Abstract: Methods of operating a memory include performing a memory access operation, obtaining an address corresponding to a subsequent memory access operation prior to stopping the memory access operation, stopping the memory access operation, sharing charge between access lines used for the memory access operation and access lines to be used for the subsequent memory access operation, and performing the subsequent memory access operation.