公开(公告)号：US20210012823A1

公开(公告)日：2021-01-14

申请号：US16506641

申请日：2019-07-09

Applicant: Arm Limited

Inventor： Piyush Jain ,  Surya Prakash Gupta ,  El Mehdi Boujamaa ,  Cyrille Nicolas Dray ,  Akshay Kumar

IPC: G11C11/16

Abstract: Various implementations described herein are directed to device having a memory block and a sense amplifier coupled to the memory block. The device may include a bias generator that applies a bias signal to the sense amplifier for regulating read current to the sense amplifier for faster activation of the memory block.

公开(公告)号：US11081156B2

公开(公告)日：2021-08-03

申请号：US16504072

申请日：2019-07-05

Applicant: Arm Limited

Inventor： Surya Prakash Gupta ,  El Mehdi Boujamaa ,  Cyrille Nicolas Dray ,  Piyush Jain ,  Akshay Kumar

IPC: G11C11/16

Abstract: Various implementations described herein are directed to device having a clock generator that provides write reference signals. The device may include a voltage divider that receives the write reference signals and provides an output reference signal based on write polarity of the write reference signals. The device may include a voltage regulator that receives the output reference signal and provides a regulated voltage to a load based on the output reference signal.

公开(公告)号：US20200286538A1

公开(公告)日：2020-09-10

申请号：US16293465

申请日：2019-03-05

Applicant: Arm Limited

Inventor： Surya Prakash Gupta ,  Piyush Jain ,  El Mehdi Boujamaa

IPC: G11C11/16

Abstract: Various implementations described herein refer to an integrated circuit having a sense amplifier that operates with a clock signal, and the sense amplifier may be biased with a bias signal that affects duration of the clock signal. The integrated circuit may include a delay circuit coupled to the sense amplifier, and the delay circuit may turn-off the clock signal. The delay circuit may have a current-starved delay stage that receives an input signal having a falling edge and provides a current-starved delay signal biased by the bias signal that also biases the sense amplifier.

公开(公告)号：US11164616B2

公开(公告)日：2021-11-02

申请号：US16506641

申请日：2019-07-09

Applicant: Arm Limited

Inventor： Piyush Jain ,  Surya Prakash Gupta ,  El Mehdi Boujamaa ,  Cyrille Nicolas Dray ,  Akshay Kumar

IPC: G11C11/16 ,  H03K19/20

Abstract: Various implementations described herein are directed to device having a memory block and a sense amplifier coupled to the memory block. The device may include a bias generator that applies a bias signal to the sense amplifier for regulating read current to the sense amplifier for faster activation of the memory block.

公开(公告)号：US20210005237A1

公开(公告)日：2021-01-07

申请号：US16504072

申请日：2019-07-05

Applicant: Arm Limited

Inventor： Surya Prakash Gupta ,  El Mehdi Boujamaa ,  Cyrille Nicolas Dray ,  Piyush Jain ,  Akshay Kumar

IPC: G11C11/16

Abstract: Various implementations described herein are directed to device having a clock generator that provides write reference signals. The device may include a voltage divider that receives the write reference signals and provides an output reference signal based on write polarity of the write reference signals. The device may include a voltage regulator that receives the output reference signal and provides a regulated voltage to a load based on the output reference signal.

公开(公告)号：US10854264B2

公开(公告)日：2020-12-01

申请号：US16293465

申请日：2019-03-05

Applicant: Arm Limited

Inventor： Surya Prakash Gupta ,  Piyush Jain ,  El Mehdi Boujamaa

IPC: G11C7/00 ,  G11C11/16

Abstract: Various implementations described herein refer to an integrated circuit having a sense amplifier that operates with a clock signal, and the sense amplifier may be biased with a bias signal that affects duration of the clock signal. The integrated circuit may include a delay circuit coupled to the sense amplifier, and the delay circuit may turn-off the clock signal. The delay circuit may have a current-starved delay stage that receives an input signal having a falling edge and provides a current-starved delay signal biased by the bias signal that also biases the sense amplifier.