公开(公告)号：US20190384501A1

公开(公告)日：2019-12-19

申请号：US16152485

申请日：2018-10-05

Applicant: Arm Limited

Inventor： Radhika Sanjeev JAGTAP ,  Nikos NIKOLERIS ,  Andreas Lars SANDBERG

IPC: G06F3/06

Abstract: An apparatus comprises control circuitry to control access to a memory implemented using a memory technology providing variable access latency. The control circuitry has request handling circuitry to identify an execution context switch comprising a transition from servicing memory access requests associated with a first execution context to servicing memory access requests associated with a second execution context. At least when the execution context switch meets a predetermined condition, a delay masking action is triggered to control subsequent memory access requests associated with the second execution context, for which the required data is already stored in the memory, to be serviced with a response delay which is independent of which addresses were accessed by the memory access requests associated with the first execution context. This can help guard against attacks which aim to exploit variation in response latency to gain insight into the addresses accessed by a victim execution context.

公开(公告)号：US20200034303A1

公开(公告)日：2020-01-30

申请号：US16142330

申请日：2018-09-26

Applicant: Arm Limited

Inventor： Radhika Sanjeev JAGTAP ,  Nikos NIKOLERIS ,  Andreas Lars SANDBERG ,  Stephan DIESTELHORST

IPC: G06F12/0864 ,  G06F12/1045

Abstract: Aspects of the present disclosure relate to an apparatus comprising a data array having locality-dependent latency characteristics such that an access to an open unit of the data array has a lower latency than an access to a closed unit of the data array. Set associative cache indexing circuitry determines, in response to a request for data associated with a target address, a cache set index. Mapping circuitry identifies, in response to the index, a set of data array locations corresponding to the index, according to a mapping in which a given unit of the data array comprises locations corresponding to a plurality of consecutive indices, and at least two locations of the set of locations corresponding to the same index are in different units of the data array. Cache access circuitry accesses said data from one of the set of data array locations.