公开(公告)号：US20190155742A1

公开(公告)日：2019-05-23

申请号：US16169219

申请日：2018-10-24

Applicant: Arm Limited

Inventor： Prakash S. RAMRAKHYANI ,  Andreas Lars SANDBERG ,  Nikos NIKOLERIS ,  Stephan DIESTELHORST

IPC: G06F12/10

Abstract: There is provided an apparatus that includes an input address port to receive an input address from processor circuitry. Address storage stores a translation between the input address and an output address in an output address space. An output address port outputs the output address. An input data port receives data. Data storage stores the data. An output data port outputs the data stored in the data storage and control circuitry causes the data storage to store the translation between the input address and the output address. The control circuitry issues a signal to cause a page walk to occur in response to the input address being absent from the address storage and the data storage.

公开(公告)号：US20230342150A1

公开(公告)日：2023-10-26

申请号：US18245840

申请日：2020-11-26

Applicant: Arm Limited

Inventor： Ilias VOUGIOUKAS ,  Andreas Lars SANDBERG ,  Nikos NIKOLERIS

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30061 ,  G06F9/30036 ,  G06F9/3804

Abstract: Apparatuses and methods for branch prediction are provided. Branch prediction circuitry generates prediction with respect to branch instructions of whether those branches will be taken or not-taken. Hypervector generation circuitry assigns an arbitrary hypervector in deterministic dependence on an address of each branch instruction, wherein the hypervectors comprises at least 500 bits. Upon the resolution of a branch a corresponding hypervector is added to a stored taken hypervector or a stored not-taken hypervector in dependence on the resolution of the branch. The branch prediction circuitry generates a prediction for a branch instructions in dependence on a mathematical distance metric of a hypervector generated for that branch instruction from the stored taken hypervector or the not-taken hypervector.

公开(公告)号：US20200034303A1

公开(公告)日：2020-01-30

申请号：US16142330

申请日：2018-09-26

Applicant: Arm Limited

Inventor： Radhika Sanjeev JAGTAP ,  Nikos NIKOLERIS ,  Andreas Lars SANDBERG ,  Stephan DIESTELHORST

IPC: G06F12/0864 ,  G06F12/1045

Abstract: Aspects of the present disclosure relate to an apparatus comprising a data array having locality-dependent latency characteristics such that an access to an open unit of the data array has a lower latency than an access to a closed unit of the data array. Set associative cache indexing circuitry determines, in response to a request for data associated with a target address, a cache set index. Mapping circuitry identifies, in response to the index, a set of data array locations corresponding to the index, according to a mapping in which a given unit of the data array comprises locations corresponding to a plurality of consecutive indices, and at least two locations of the set of locations corresponding to the same index are in different units of the data array. Cache access circuitry accesses said data from one of the set of data array locations.

公开(公告)号：US20190384718A1

公开(公告)日：2019-12-19

申请号：US16464019

申请日：2017-09-15

Applicant: ARM LIMITED

Inventor： Andreas HANSSON ,  Nikos NIKOLERIS ,  Wendy Arnott ELSASSER

IPC: G06F12/0895 ,  G06F12/0864 ,  G11C11/406 ,  G11C11/16

Abstract: Storage circuitry comprises an array of storage locations arranged in rows and columns, a row buffer comprising a plurality of entries each to store information from a storage location at a corresponding column of an active row of the array, and comparison circuitry responsive to a tag-matching command specifying a tag value to compare the tag value with information stored in each of a subset of two or more entries of the row buffer. The comparison circuitry identifies which of the subset of entries, if any, is a matching entry storing information matching the tag value. This allows memory technologies such as DRAM to be used more efficiently as a set-associative cache.

公开(公告)号：US20180157437A1

公开(公告)日：2018-06-07

申请号：US15806580

申请日：2017-11-08

Applicant: ARM LIMITED

Inventor： Andreas Lars SANDBERG ,  Nikos NIKOLERIS ,  David Hennah MANSELL

IPC: G06F3/06 ,  G06F12/10

CPC classification number: G06F3/0647 ,  G06F3/0611 ,  G06F3/0673 ,  G06F12/0831 ,  G06F12/10 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/1024

Abstract: An apparatus and method are provided for transferring data between address ranges in memory. The apparatus comprises a data transfer controller, that is responsive to a data transfer request received by the apparatus from a processing element, to perform a transfer operation to transfer data from at least one source address range in memory to at least one destination address range in the memory. A redirect controller is then arranged, whilst the transfer operation is being performed, to intercept an access request that specifies a target address within a target address range, and to perform a memory redirection operation so as to cause the access request to be processed without awaiting completion of the transfer operation. Via such an approach, the apparatus can effectively hide from the source of the access request the fact that the transfer operation is in progress, and hence the transfer operation can be arranged to occur in the background, and in a manner that is transparent to the software executing on the source that has issued the access request.

公开(公告)号：US20200264980A1

公开(公告)日：2020-08-20

申请号：US16865642

申请日：2020-05-04

Applicant: ARM Limited

Inventor： Wei WANG ,  Stephan DIESTELHORST ,  Wendy Arnott ELSASSER ,  Andreas Lars SANDBERG ,  Nikos NIKOLERIS

IPC: G06F12/0873 ,  G06F12/0868 ,  G06F12/126 ,  G06F11/14 ,  G11C5/14 ,  G06F12/02 ,  G06F12/0895 ,  G06F1/3206 ,  G06F12/0871

Abstract: An apparatus and method are provided for handling caching of persistent data. The apparatus comprises cache storage having a plurality of entries to cache data items associated with memory address in a non-volatile memory. The data items may comprise persistent data items and non-persistent data items. Write back control circuitry is used to control write back of the data items from the cache storage to the non-volatile memory. In addition, cache usage determination circuitry is used to determine, in dependence on information indicative of capacity of a backup energy source, a subset of the plurality of entries to be used to store persistent data items. In response to an event causing the backup energy source to be used, the write back control circuitry is then arranged to initiate write back to the non-volatile memory of the persistent data items cached in the subset of the plurality of entries. By constraining the extent to which the cache storage is allowed to store persistent data items, taking into account the capacity of the backup energy source, the persistence of those data items can then be guaranteed in the event of the backup energy source being triggered, for example due to removal of the primary energy source for the apparatus.

公开(公告)号：US20190384501A1

公开(公告)日：2019-12-19

申请号：US16152485

申请日：2018-10-05

Applicant: Arm Limited

Inventor： Radhika Sanjeev JAGTAP ,  Nikos NIKOLERIS ,  Andreas Lars SANDBERG

IPC: G06F3/06

Abstract: An apparatus comprises control circuitry to control access to a memory implemented using a memory technology providing variable access latency. The control circuitry has request handling circuitry to identify an execution context switch comprising a transition from servicing memory access requests associated with a first execution context to servicing memory access requests associated with a second execution context. At least when the execution context switch meets a predetermined condition, a delay masking action is triggered to control subsequent memory access requests associated with the second execution context, for which the required data is already stored in the memory, to be serviced with a response delay which is independent of which addresses were accessed by the memory access requests associated with the first execution context. This can help guard against attacks which aim to exploit variation in response latency to gain insight into the addresses accessed by a victim execution context.

公开(公告)号：US20190155748A1

公开(公告)日：2019-05-23

申请号：US16181474

申请日：2018-11-06

Applicant: Arm Limited

Inventor： Andreas Lars SANDBERG ,  Nikos NIKOLERIS ,  Prakash S. RAMRAKHYANI

IPC: G06F12/1027

Abstract: Memory address translation apparatus comprises page table access circuitry to access page table data to retrieve translation data defining an address translation between an initial memory address in an initial memory address space, and a corresponding output memory address in an output address space; a translation data buffer to store, for a subset of the virtual address space, one or more instances of the translation data; and control circuitry, responsive to an input initial memory address to be translated, to request retrieval of translation data for the input initial memory address from the translation data buffer and, before completion of processing of the request for retrieval from the translation data buffer, to initiate retrieval of translation data for the input initial memory address by the page table access circuitry.

公开(公告)号：US20190155747A1

公开(公告)日：2019-05-23

申请号：US16169206

申请日：2018-10-24

Applicant: Arm Limited

Inventor： Andreas Lars SANDBERG ,  Nikos NIKOLERIS ,  Prakash S. RAMRAKHYANI ,  Stephan DIESTELHORST

IPC: G06F12/1027 ,  G06F12/02 ,  G06F12/0808 ,  G06F12/06 ,  G06F13/16 ,  G06F3/06

Abstract: There is provided an apparatus that includes an input port to receive, from a requester, any one of: a lookup operation comprising an input address, and a maintenance operation. Maintenance queue circuitry stores a maintenance queue of at least one maintenance operation and address storage stores a translation between the input address and an output address in an output address space. In response to receiving the input address, the output address is provided in dependence on the maintenance queue. In response to storing the maintenance operation, the maintenance queue circuitry causes an acknowledgement to be sent to the requester. By providing a separate maintenance queue for performing the maintenance operation, there is no need for a requester to be blocked while maintenance is performed.

公开(公告)号：US20190004960A1

公开(公告)日：2019-01-03

申请号：US16005934

申请日：2018-06-12

Applicant: ARM Limited

Inventor： Wei Wang ,  Stephan Diestelhorst ,  Wendy Arnott ELSASSER ,  Andreas Lars Sandberg ,  Nikos NIKOLERIS

IPC: G06F12/0873 ,  G06F12/0871 ,  G06F12/02 ,  G06F12/0895 ,  G06F1/32

Abstract: An apparatus and method are provided for handling caching of persistent data. The apparatus comprises cache storage having a plurality of entries to cache data items associated with memory address in a non-volatile memory. The data items may comprise persistent data items and non-persistent data items. Write back control circuitry is used to control write back of the data items from the cache storage to the non-volatile memory. In addition, cache usage determination circuitry is used to determine, in dependence on information indicative of capacity of a backup energy source, a subset of the plurality of entries to be used to store persistent data items. In response to an event causing the backup energy source to be used, the write back control circuitry is then arranged to initiate write back to the non-volatile memory of the persistent data items cached in the subset of the plurality of entries. By constraining the extent to which the cache storage is allowed to store persistent data items, taking into account the capacity of the backup energy source, the persistence of those data items can then be guaranteed in the event of the backup energy source being triggered, for example due to removal of the primary energy source for the apparatus.