-
公开(公告)号：US10901691B2
公开(公告)日：2021-01-26
申请号：US16261071
申请日：2019-01-29
Applicant: Arm Limited
Abstract: A system, apparatus and method for enabling a FIFO-like (first-in-first-out) communication between a plurality of executing processes that are distributed throughout a computing system. Embodiments exploit locality in the hierarchy of the cache memory and communication busses within the computing system to enable the passing of messages or streams of bytes with a low latency and high throughput. In addition, this allows for participating components to be very simple, or very sophisticated, but still benefit from the improved communications patterns.
-
公开(公告)号：US12229565B2
公开(公告)日：2025-02-18
申请号：US18042845
申请日：2021-08-26
Applicant: ARM LIMITED
Inventor： Syed Ali Mustafa Zaidi , Giacomo Gabrielli
Abstract: A data processing apparatus and a method for processing data are disclosed. The data processing apparatus comprises: multithreaded processing circuitry to perform processing operations of a plurality of micro-threads, each micro-thread operating in a corresponding execution context defining an architectural state. Thread control circuitry collects runtime data indicative of a performance metric relating to the processing operations. Decoder circuitry is responsive to a detach instruction in a first micro-thread of instructions executed in a first execution context defining a first architectural state, the detach instruction specifying an address, to provide detach control signals to the thread control circuitry. When the runtime data meet a parallelization criterion, the thread control circuitry is responsive to the detach control signals to spawn a second micro-thread of instructions executed in a second execution context defining a second architectural state based on the first architectural state, the second micro-thread of instructions comprising a subset of instructions of the first micro-thread of instructions starting at the address.
-
公开(公告)号：US11086626B2
公开(公告)日：2021-08-10
申请号：US16662396
申请日：2019-10-24
Applicant: Arm Limited
Inventor： Roko Grubisic , Giacomo Gabrielli , Matthew James Horsnell , Syed Ali Mustafa Zaidi
Abstract: Circuitry comprises decode circuitry to decode program instructions including producer instructions and consumer instructions, a consumer instruction requiring, as an input operand, a result generated by execution of a producer instruction; and execution circuitry to execute the program instructions; in which: the decode circuitry is configured to control operation of the execution circuitry in response to hint data associated with a given producer instruction and indicating, for the given producer instruction, a number of consumer instructions which require, as an input operand, a result generated by the given producer instruction.
-
公开(公告)号：US20200241839A1
公开(公告)日：2020-07-30
申请号：US16261071
申请日：2019-01-29
Applicant: Arm Limited
Abstract: A system, apparatus and method for enabling a FIFO-like (first-in-first-out) communication between a plurality of executing processes that are distributed throughout a computing system. Embodiments exploit locality in the hierarchy of the cache memory and communication busses within the computing system to enable the passing of messages or streams of bytes with a low latency and high throughput. In addition, this allows for participating components to be very simple, or very sophisticated, but still benefit from the improved communications patterns.
-
-
-
Search Results
4
records
(took 0.011 seconds)
