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公开(公告)号：US11481290B2
公开(公告)日：2022-10-25
申请号：US17046396
申请日：2019-04-08
申请人： Arm Limited
摘要： An apparatus and a method of operating a data processing apparatus, and simulators thereof, are disclosed. Data processing circuitry performs data processing operations in response to instructions, where some sets of instructions may be defined as a transaction which are to be performed atomically with respect to other operations performed by the data processing circuitry. When a synchronous exception occurs during a transaction the transaction is aborted and an exception counter is incremented. When the counter reaches a threshold value a transaction failure signal is generated, allowing, if appropriate a response to this number of exceptions causing transaction aborts to be carried out.
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公开(公告)号：US10908944B2
公开(公告)日：2021-02-02
申请号：US15532221
申请日：2015-11-24
申请人： ARM Limited
摘要： An apparatus (2) with multiple processing elements (4, 6, 8) has shared transactional processing resources (10, 50, 75) for supporting processing of transactions, which comprise operations performed speculatively following a transaction start event whose results are committed following a transaction end event. The transactional processing resources may have a significant overhead and sharing these between the processing elements helps reduce energy consumption and circuit area.
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公开(公告)号：US10810039B2
公开(公告)日：2020-10-20
申请号：US15537015
申请日：2015-11-24
申请人： ARM LIMITED
摘要： An apparatus (2) may have a processing element (4) for performing data access operations to access data from at least one storage device (10, 12, 14). The processing element may have at least one transactional processing resource (10, 18) supporting processing of a transaction in which data accesses are performed speculatively following a transaction start event and for which the speculative results are committed in response to a transaction end event. Monitoring circuitry (30) captures monitoring data indicating a degree of utilization of the transactional processing resource (10, 18) when processing the transaction.
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公开(公告)号：US20200257787A1
公开(公告)日：2020-08-13
申请号：US16271760
申请日：2019-02-08
申请人： Arm Limited
发明人： Mbou Eyole , Matthew James Horsnell
IPC分类号： G06F21/36 , A61B5/117 , A61B5/0484 , A61B5/00
摘要： Briefly, example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, using one or more processing devices to facilitate and/or support one or more operations and/or techniques for authenticating an identity of a human subject. In particular, some embodiments are directed to techniques for authentication of an identity of a human subject as being an identity of a particular unique individual based, at least in part, on involuntary responses by the human subject to sensory stimuli.
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公开(公告)号：US10678595B2
公开(公告)日：2020-06-09
申请号：US15324082
申请日：2015-06-11
申请人： ARM LIMITED
摘要： A data processing apparatus comprises a plurality of data storage elements, each configured to store data. Mask storage circuitry stores a mask and processing circuitry executes one or more instructions. A data saver is configured, in response to a transactional start instruction, to select a subset of the data storage elements and to save a backup of the subset of the data storage elements. Mask control circuitry then updates the mask to indicate the subset of the data storage elements selected by the data saver. Finally, a monitor detects write or write attempts made to one of the data storage elements not indicated by the mask. Accordingly, a user need not save all data storage elements (e.g. registers) in a system or specify precisely which data storage elements must be saved in order to perform a transaction. Instead, the set of data storage elements that must be saved can be determined and specified dynamically, and the system can respond if an attempt is made to write to a data storage element that has not been saved or backed up.
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公开(公告)号：US10572299B2
公开(公告)日：2020-02-25
申请号：US15531836
申请日：2015-11-24
申请人： ARM LIMITED
摘要： An apparatus (2) has processing circuitry (6) having access to a first processing resource (20-0) and a second processing resource (20-3). A first thread can be processed using the first processing resource. In a thread mode the second processing resource (20-3) can be used to process a second thread while in a transaction mode the second processing resource (20-3) can be used to process a transaction of the first thread comprising a number of speculatively performed operations for which results are committed at the end of the transaction. By sharing resources for supporting additional threads and supporting transactions, circuit area and power consumption can be reduced.
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公开(公告)号：US11663034B2
公开(公告)日：2023-05-30
申请号：US16651017
申请日：2018-08-21
申请人： Arm Limited
CPC分类号： G06F9/467 , G06F9/3009 , G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F9/466 , G06F9/4812 , G06F11/1402 , G06F11/1474
摘要： A data processing apparatus has processing circuitry with transactional memory support circuitry to support execution of a transaction using transactional memory. In response to an exception mask updating instruction which updates exception mask information to enable at least one subset of exceptions which was disabled at the start of processing of a transaction, the processing circuitry permits un-aborted processing of one or more subsequent instruction of the transaction that follow the exception mask update instruction.
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公开(公告)号：US11422808B2
公开(公告)日：2022-08-23
申请号：US17258287
申请日：2019-05-09
申请人： Arm Limited
摘要： An apparatus comprising: processing circuitry to process threads of data processing; and transactional memory support circuitry to support execution of a transaction within a thread processed by the processing circuitry. In response to a transactional compare-and-discard instruction executed within a given transaction, specifying a target address and a compare value, the processing circuitry loads a target data value from a memory location corresponding to the target address; sets at least one condition status indication depending on a result of comparing the target data value and the compare value; and discards the target data value without adding the target address to a working set of addresses tracked for the given transaction. This is useful for enabling thread level speculation to be implemented on a transactional memory architecture.
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公开(公告)号：US11347539B2
公开(公告)日：2022-05-31
申请号：US16651178
申请日：2018-08-30
申请人： ARM Limited
摘要： In an apparatus (2) with transactional memory support, a predetermined type of transaction start instruction or a subsequent instruction following the predetermined type of transaction start instruction triggers capture of a lock identifier which identifies a lock variable for controlling exclusive access to at least one resource. In response to a predetermined type of transaction end instruction which follows the predetermined type of transaction start instruction, the lock variable is checked and commitment of results of speculatively executed instructions of the transaction is prevented or deferred when the lock variable indicates that another thread holds the exclusive access to the target resource. This approach can improve performance when executing transactions in a transactional memory based system.
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公开(公告)号：US20220129534A1
公开(公告)日：2022-04-28
申请号：US17429222
申请日：2019-07-26
申请人： Arm Limited , Apical Limited
摘要： Briefly, example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, using one or more processing devices to facilitate and/or support one or more operations and/or techniques for authenticating an identity of a subject. In particular, some embodiments are directed to techniques for authentication of an identity of a subject as being an identity of a particular unique individual based, at least in part, on involuntary responses by the subject to sensory stimuli.
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