公开(公告)号：US11687464B2

公开(公告)日：2023-06-27

申请号：US16648041

申请日：2019-01-23

Applicant: ARM LIMITED

Inventor： Graeme Peter Barnes ,  Catalin Theodor Marinas ,  William James Deacon

IPC: G06F12/10

CPC classification number: G06F12/10 ,  G06F2212/657

Abstract: An apparatus comprises address translation circuitry (70) to perform a translation of a virtual address (80) comprising a virtual tag portion (88) and a virtual address portion (86) into a physical address (82) comprising a physical tag portion (92) and a physical address portion (90). The address translation circuitry comprises address tag translation circuitry (72) to perform a translation of the virtual tag portion into the physical tag portion and the address translation to be performed is selected in dependence on the virtual address.

公开(公告)号：US11842195B2

公开(公告)日：2023-12-12

申请号：US17310784

申请日：2020-01-07

Applicant: Arm Limited

Inventor： William James Deacon ,  Marc Zyngier

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/455 ,  G06F12/1009

CPC classification number: G06F9/30145 ,  G06F9/30072 ,  G06F9/30189 ,  G06F9/3836 ,  G06F9/45558 ,  G06F12/1009 ,  G06F2009/45583

Abstract: An apparatus comprises processing circuitry which has a hypervisor execution mode for execution of a hypervisor for managing one or more virtual processors executing on the processing circuitry, and at least one less privileged execution mode than the hypervisor execution mode. In response to a conditional yield to hypervisor instruction executed in the at least one less privileged execution mode, an instruction decoder controls the processing circuitry to determine whether at least one trap condition is satisfied, and when the at least one trap condition is determined to be satisfied, to switch the processing circuitry to the hypervisor execution mode; and store, in at least one storage element accessible to instructions executed in the hypervisor execution mode, at least one item of scheduling hint information for estimating whether the at least one trap condition is still satisfied.