公开(公告)号：US10747845B2

公开(公告)日：2020-08-18

申请号：US16118818

申请日：2018-08-31

Applicant: Arm Limited

Inventor： Paul Nicholas Whatmough ,  Matthew Mattina ,  Zhigang Liu

IPC: G06F17/16 ,  G06F7/523 ,  G06N3/04 ,  G06N3/08

Abstract: A system, apparatus and method for exposing input data operands and input weight operands to elements of a two-dimensional array so that two pairs of operands are exposed to each element of the array.

公开(公告)号：US11379556B2

公开(公告)日：2022-07-05

申请号：US16417937

申请日：2019-05-21

Applicant: Arm Limited

Inventor： Matthew Mattina ,  Zhigang Liu ,  Paul Nicholas Whatmough ,  David Hennah Mansell

IPC: G06F17/16

Abstract: There is provided a data processing apparatus to perform an operation on a first matrix and a second matrix. The data processing apparatus includes receiver circuitry to receive elements of the first matrix, elements of the second matrix, and correspondence data to indicate where the elements of the first matrix are located in the first matrix. Determination circuitry performs, using the correspondence data, a determination of whether, for a given element of the first matrix in column i of the first matrix, a given element of the second matrix occurs in row i of the second matrix. Aggregation circuitry calculates an aggregation between a given row in the first matrix and a given column in the second matrix and includes: functional circuitry to perform, in dependence on the determination, a function on the given element of the first matrix and the given element of the second matrix to produce a partial result.

公开(公告)号：US20200073911A1

公开(公告)日：2020-03-05

申请号：US16118818

申请日：2018-08-31

Applicant: Arm Limited

Inventor： Paul Nicholas Whatmough ,  Matthew Mattina ,  Zhigang Liu

IPC: G06F17/16 ,  G06N3/08 ,  G06N3/04 ,  G06F7/523

Abstract: A system, apparatus and method for exposing input data operands and input weight operands to elements of a two-dimensional array so that two pairs of operands are exposed to each element of the array.

公开(公告)号：US20200326938A1

公开(公告)日：2020-10-15

申请号：US16381349

申请日：2019-04-11

Applicant: Arm Limited

Inventor： Zhigang Liu ,  Matthew Mattina ,  Paul Nicholas Whatmough ,  Jesse Garrett Beu

IPC: G06F9/30 ,  G06F17/16 ,  G06F9/38

Abstract: A data processor receives a first set of processor instructions for combining a first matrix with a second matrix to produce a third matrix and generates a second set of processor instructions therefrom by identifying values of non-zero elements of the first matrix stored in a memory of the data processor and determining memory locations of elements of the second matrix. An instruction of the second set of processor instructions includes a determined memory location and/or an explicit value of an identified non-zero element. The second set of processor instructions is executed by the data processor. The second set of processor instructions may be generated by just-in-time compilation of the first set of processor instructions and may include instructions of a custom instruction set architecture.