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1.发明公开公开(公告)号：US20240046065A1
公开(公告)日：2024-02-08
申请号：US17817142
申请日：2022-08-03
申请人： Arm Limited
发明人： Hokchhay Tann , Ramon Matas Navarro , Igor Fedorov , Chuteng Zhou , Paul Nicholas Whatmough , Matthew Mattina
IPC分类号： G06N3/04
CPC分类号： G06N3/04
摘要： Example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, using one or more computing devices to determine options for decisions in connection with design features of a computing device. In a particular implementation, design options for two or more design decisions of neural network processing device may be identified based, at least in part, on combination of a definition of available computing resources and one or more predefined performance constraints.
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公开(公告)号：US11886972B2
公开(公告)日：2024-01-30
申请号：US17036490
申请日：2020-09-29
申请人： Arm Limited
IPC分类号： G06N3/04 , G11C13/00 , G06F7/544 , H03M1/12 , H03M1/66 , G06N3/065 , G06N3/045 , G06N3/048 , G11C11/54 , G06N3/044
CPC分类号： G06N3/04 , G06F7/5443 , G06N3/045 , G06N3/048 , G06N3/065 , G11C11/54 , G11C13/0007 , G11C13/0069 , G06N3/044 , H03M1/12 , H03M1/66
摘要： A non-volatile memory (NVM) crossbar for an artificial neural network (ANN) accelerator is provided. The NVM crossbar includes row signal lines configured to receive input analog voltage signals, multiply-and-accumulate (MAC) column signal lines, a correction column signal line, a MAC cell disposed at each row signal line and MAC column signal line intersection, and a correction cell disposed at each row signal line and correction column signal line intersection. Each MAC cell includes one or more programmable NVM elements programmed to an ANN unipolar weight, and each correction cell includes one or more programmable NVM elements. Each MAC column signal line generates a MAC signal based on the input analog voltage signals and the respective MAC cells, and the correction column signal line generates a correction signal based on the input analog voltage signals and the correction cells. Each MAC signal is corrected based on the correction signal.
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公开(公告)号：US20230297432A1
公开(公告)日：2023-09-21
申请号：US17697706
申请日：2022-03-17
申请人： Arm Limited
摘要： Various implementations described herein are related to a method that monitors workloads of a neural network for current spikes. The method may determine current transitions of the workloads that result in rapid changes in load current consumption of the neural network. The method may modify load scheduling of the neural network so as to smooth and/or stabilize the current transitions of the workloads.
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公开(公告)号：US11693796B2
公开(公告)日：2023-07-04
申请号：US17334960
申请日：2021-05-31
申请人： Arm Limited
发明人： Paul Nicholas Whatmough , Zhi-Gang Liu , Supreet Jeloka , Saurabh Pijuskumar Sinha , Matthew Mattina
CPC分类号： G06F13/1668 , G06F13/4004 , G06F7/5443 , G06F15/8046 , G06N3/063
摘要： Various implementations described herein are directed to a device having a multi-layered logic structure with a first logic layer and a second logic layer arranged vertically in a stacked configuration. The device may have a memory array that provides data, and also, the device may have an inter-layer data bus that vertically couples the memory array to the multi-layered logic structure. The inter-layer data bus may provide multiple data paths to the first logic layer and the second logic layer for reuse of the data provided by the memory array.
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公开(公告)号：US20230076138A1
公开(公告)日：2023-03-09
申请号：US17470470
申请日：2021-09-09
申请人： Arm Limited
摘要： A matrix multiplication system and method are provided. The system includes a memory that stores one or more weight tensors, a processor and a matrix multiply accelerator (MMA). The processor converts each weight tensor into an encoded block set that is stored in the memory. Each encoded block set includes a number of encoded blocks, and each encoded block includes a data field and an index field. The MMA converts each encoded block set into a reconstructed weight tensor, and convolves each reconstructed weight tensor and an input data tensor to generate an output data matrix.
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公开(公告)号：US20230042271A1
公开(公告)日：2023-02-09
申请号：US17394048
申请日：2021-08-04
申请人： Arm Limited
发明人： Igor Fedorov , Ramon Matas Navarro , Chuteng Zhou , Hokchhay Tann , Paul Nicholas Whatmough , Matthew Mattina
摘要： Example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, using one or more computing devices to select options for decisions in connection with design features of a computing device. In a particular implementation, design options for two or more design decisions of neural network processing device may be selected based, at least in part, on combination of function values that are computed based, at least in part, on a tensor expressing sample neural network weights.
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公开(公告)号：US20210192323A1
公开(公告)日：2021-06-24
申请号：US16720380
申请日：2019-12-19
申请人： Arm Limited
摘要： The present disclosure advantageously provides a hardware accelerator for an artificial neural network (ANN), including a communication bus interface, a memory, a controller, and at least one processing engine (PE). The communication bus interface is configured to receive a plurality of finetuned weights associated with the ANN, receive input data, and transmit output data. The memory is configured to store the plurality of finetuned weights, the input data and the output data. The PE is configured to receive the input data, execute an ANN model using a plurality of fixed weights associated with the ANN and the plurality of finetuned weights, and generate the output data. Each finetuned weight corresponds to a fixed weight.
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公开(公告)号：US20230289576A1
公开(公告)日：2023-09-14
申请号：US17689755
申请日：2022-03-08
申请人： Arm Limited
摘要： Various implementations described herein are directed to a device having neural network circuitry with an array of synapse cells arranged in columns and rows. The device may have input circuitry that provides voltage to the synapse cells by way of row input lines for the rows in the array. The device may have output circuitry that receives current from the synapse cells by way of column output lines for the columns in the array. Also, conductance for the synapse cells in the array may be determined based on the voltage provided by the input circuitry and the current received by the output circuitry.
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公开(公告)号：US11501151B2
公开(公告)日：2022-11-15
申请号：US16885704
申请日：2020-05-28
申请人： Arm Limited
摘要： The present disclosure advantageously provides a pipelined accumulator that includes a data selector configured to receive a sequence of operands to be summed, an input register coupled to the data selector, an output register, coupled to the data selector, configured to store a sequence of partial sums and output a final sum, and a multi-stage add module coupled to the input register and the output register. The multi-stage add module is configured to store a sequence of partial sums and a final sum in a redundant format, and perform back-to-back accumulation into the output register.
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公开(公告)号：US20220180158A1
公开(公告)日：2022-06-09
申请号：US17116623
申请日：2020-12-09
申请人： Arm Limited
摘要： An artificial neural network (ANN) accelerator is provided. The ANN accelerator includes digital controlled oscillators (DCOs), digital-to-time converters (DTCs) and a mixed-signal multiply-and-accumulate (MAC) array. Each DCO generates a first analog operand signal based on a first digital data value, and transmits the first analog operand signal along a respective column signal line. Each DTC generates a second analog operand signal based on a second digital data value, and transmits the second analog operand signal along a respective row signal line. The mixed-signal MAC array is coupled to the row and column signal lines, and includes mixed-signal MAC units. Each mixed-signal MAC unit includes an integrated clock gate (ICG) that generates a digital product signal based on the first and second analog operand signals, and a counter circuit that increments or decrements a count value stored in a register based on the digital product signal.
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