公开(公告)号：US08145967B2

公开(公告)日：2012-03-27

申请号：US11974414

申请日：2007-10-12

申请人： Arvind Srinivasan ,  Rahoul Puri

发明人： Arvind Srinivasan ,  Rahoul Puri

IPC分类号： G06F11/00

CPC分类号： G06F11/277

摘要： A system and method for verifying the receive path of an input/output device such as a network interface circuit. The device's operation with various different input sources (e.g., networks) and output sources (e.g., hosts, host buses) is modeled in a verification layer that employs multiple queues to simulate receipt of packets, calculation of destination addresses and storage of the packet data by the device. Call backs are employed to signal completion of events related to storage of packet data by the device and modeling of data processing within the verification layer. Processing of tokens within the verification layer to mimic the device's processing of corresponding packets is performed according to a dynamic DMA policy modeled on the device's policy. The policy is dynamic and can be updated or replaced during verification without interrupting the verification process.

摘要翻译： 一种用于验证诸如网络接口电路的输入/输出设备的接收路径的系统和方法。 该设备利用各种不同的输入源（例如网络）和输出源（例如，主机，主机总线）的操作被建模在采用多个队列来模拟分组的接收，计算目的地址和分组数据的存储的验证层中 通过设备。 采用回叫信号来完成与设备的分组数据的存储相关的事件以及验证层内数据处理的建模。 根据设备策略建模的动态DMA策略，对验证层内的令牌进行处理以模拟设备对相应数据包的处理。 该策略是动态的，可以在验证过程中进行更新或替换，而不会中断验证过程。

公开(公告)号：US08032669B2

公开(公告)日：2011-10-04

申请号：US12017039

申请日：2008-01-20

申请人： Rahoul Puri ,  Arvind Srinivasan ,  Elisa Rodrigues

发明人： Rahoul Puri ,  Arvind Srinivasan ,  Elisa Rodrigues

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： A universal DMA (Direct Memory Access) engine can be dynamically configured to function in either a receive or transmit mode. DMAs are logically assembled and bound as needed, without limitation to a fixed, pre-determined number of receive engines and transmit engines. Because a DMA engine may be dynamically assembled to support the flow of data in either direction, varied usage models are enabled, and components used to assemble a receive DMA engine for one application may be subsequently used to assemble a transmit engine for a different application. An application may request a specific number of each type of engine, depending on the nature of its input/output traffic. The number of receive or transmit engines can be dynamically increased or decreased without suspending or rebooting the host. A universal DMA architecture provides a unified software framework, thereby decreasing the complexity of the software and the hardware gate count cost.

摘要翻译： 通用DMA（直接存储器访问）引擎可以动态配置为以接收或发送模式工作。 根据需要，逻辑上组装和绑定DMA，而不限于固定的预定数量的接收引擎和传输引擎。 因为可以动态地组装DMA引擎以支持任一方向上的数据流，所以可以使用各种使用模型，并且用于组合一个应用的接收DMA引擎的组件可以随后用于组装用于不同应用的传输引擎。 应用可以根据其输入/输出流量的性质来请求每种类型的引擎的特定数量。 接收或发送引擎的数量可以动态增加或减少，而不会挂起或重新启动主机。 通用DMA架构提供统一的软件框架，从而降低软件的复杂性和硬件门数的成本。

公开(公告)号：US20090100296A1

公开(公告)日：2009-04-16

申请号：US11974413

申请日：2007-10-12

申请人： Arvind Srinivasan ,  Rahoul Puri

发明人： Arvind Srinivasan ,  Rahoul Puri

IPC分类号： G06F11/00

CPC分类号： H04L43/50

摘要： A system and method for verifying the transmit path of an input/output device such as a network interface circuit. The device's operation with various different input sources (e.g., hosts, input buses) and output sources (e.g., output buses, networks) is modeled in a verification layer that employs multiple queues to simulate receipt of input data, submission to an output port and transmission from the device. Call backs are employed to signal completion of events related to receipt of data at the device and modeling of data processing within the verification layer. As call backs are resolved, corresponding tasks are executed to advance the processing of the data through the verification layer. A device-specific algorithm is executed in the verification layer to predict the ordering of output from the device, and that output is compared to the predicted output by a transmission checker.

摘要翻译： 一种用于验证诸如网络接口电路的输入/输出设备的发送路径的系统和方法。 该设备在各种不同的输入源（例如，主机，输入总线）和输出源（例如，输出总线，网络）中的操作被建模在验证层中，该验证层采用多个队列来模拟输入数据的接收，提交到输出端口 从设备传输。 采用回叫信号来完成与设备上的数据接收有关的事件以及验证层内的数据处理建模。 随着回叫的解决，相应的任务被执行以通过验证层来推进对数据的处理。 在验证层中执行特定于设备的算法来预测来自设备的输出的顺序，并且将该输出与传输检查器的预测输出进行比较。

公开(公告)号：US08176304B2

公开(公告)日：2012-05-08

申请号：US12256250

申请日：2008-10-22

申请人： Rahoul Puri ,  Arvind Srinivasan ,  Louise Y. Yeung ,  Marcelino M. Dignum ,  John E. Watkins

发明人： Rahoul Puri ,  Arvind Srinivasan ,  Louise Y. Yeung ,  Marcelino M. Dignum ,  John E. Watkins

IPC分类号： G06F9/00 ,  G06F15/177 ,  G06F1/24 ,  G06F3/00 ,  G06F13/00

CPC分类号： G06F13/385

摘要： An I/O device having function level reset functionality includes a host interface that may include a master reset unit, a plurality of client interfaces, each corresponding to one or more functions, and a plurality of hardware resources. Each hardware resource may be associated with a respective function. In response to receiving a reset request to reset a specific function, the master reset unit may provide to each client interface, a request signal corresponding to the reset request, and a signal identifying the specific function. Each client interface having an association with the specific function may initiate a reset operation of the associated hardware resources, and also provide a client reset done signal for the specific function to the master reset unit in response to completion of the reset operations of the hardware resources. The master reset unit provides a reset done signal for the specific function to the host interface.

摘要翻译： 具有功能级复位功能的I / O设备包括主机接口，其可以包括主复位单元，多个客户端接口，每个对应于一个或多个功能，以及多个硬件资源。 每个硬件资源可以与相应的功能相关联。 响应于接收到重置特定功能的复位请求，主复位单元可以向每个客户端接口提供对应于重置请求的请求信号，以及标识特定功能的信号。 具有与特定功能的关联的每个客户端接口可以启动相关联的硬件资源的复位操作，并且响应于硬件资源的复位操作的完成，向主复位单元提供用于特定功能的客户端重置完成信号 。 主复位单元为主机接口提供特定功能的复位完成信号。

公开(公告)号：US20100100717A1

公开(公告)日：2010-04-22

申请号：US12256250

申请日：2008-10-22

申请人： Rahoul Puri ,  Arvind Srinivasan ,  Louise Y. Yeung ,  Marcelino M. Dignum ,  John E. Watkins

发明人： Rahoul Puri ,  Arvind Srinivasan ,  Louise Y. Yeung ,  Marcelino M. Dignum ,  John E. Watkins

IPC分类号： G06F9/00

CPC分类号： G06F13/385

摘要： An I/O device having function level reset functionality includes a host interface that may include a master reset unit, a plurality of client interfaces, each corresponding to one or more functions, and a plurality of hardware resources. Each hardware resource may be associated with a respective function. In response to receiving a reset request to reset a specific function, the master reset unit may provide to each client interface, a request signal corresponding to the reset request, and a signal identifying the specific function. Each client interface having an association with the specific function may initiate a reset operation of the associated hardware resources, and also provide a client reset done signal for the specific function to the master reset unit in response to completion of the reset operations of the hardware resources. The master reset unit provides a reset done signal for the specific function to the host interface.

摘要翻译： 具有功能级复位功能的I / O设备包括主机接口，其可以包括主复位单元，多个客户端接口，每个对应于一个或多个功能，以及多个硬件资源。 每个硬件资源可以与相应的功能相关联。 响应于接收到重置特定功能的复位请求，主复位单元可以向每个客户端接口提供对应于重置请求的请求信号，以及标识特定功能的信号。 具有与特定功能的关联的每个客户端接口可以启动相关联的硬件资源的复位操作，并且响应于硬件资源的复位操作的完成，向主复位单元提供用于特定功能的客户端重置完成信号 。 主复位单元为主机接口提供特定功能的复位完成信号。

公开(公告)号：US20090187679A1

公开(公告)日：2009-07-23

申请号：US12017039

申请日：2008-01-20

申请人： Rahoul Puri ,  Arvind Srinivasan ,  Elisa Rodrigues

发明人： Rahoul Puri ,  Arvind Srinivasan ,  Elisa Rodrigues

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： A universal DMA (Direct Memory Access) engine can be dynamically configured to function in either a receive or transmit mode. DMAs are logically assembled and bound as needed, without limitation to a fixed, pre-determined number of receive engines and transmit engines. Because a DMA engine may be dynamically assembled to support the flow of data in either direction, varied usage models are enabled, and components used to assemble a receive DMA engine for one application may be subsequently used to assemble a transmit engine for a different application. An application may request a specific number of each type of engine, depending on the nature of its input/output traffic. The number of receive or transmit engines can be dynamically increased or decreased without suspending or rebooting the host. A universal DMA architecture provides a unified software framework, thereby decreasing the complexity of the software and the hardware gate count cost.

摘要翻译： 通用DMA（直接存储器访问）引擎可以动态配置为以接收或发送模式工作。 根据需要，逻辑上组装和绑定DMA，而不限于固定的预定数量的接收引擎和传输引擎。 因为可以动态地组装DMA引擎以支持任一方向上的数据流，所以可以使用各种使用模型，并且用于组合一个应用的接收DMA引擎的组件可以随后用于组装用于不同应用的传输引擎。 应用可以根据其输入/输出流量的性质来请求每种类型的引擎的特定数量。 接收或发送引擎的数量可以动态增加或减少，而不会挂起或重新启动主机。 通用DMA架构提供统一的软件框架，从而降低软件的复杂性和硬件门数的成本。

公开(公告)号：US20090168657A1

公开(公告)日：2009-07-02

申请号：US11967225

申请日：2007-12-30

申请人： Rahoul Puri ,  Arvind Srinivasan ,  Saranga P. Pogula

发明人： Rahoul Puri ,  Arvind Srinivasan ,  Saranga P. Pogula

IPC分类号： G06F11/00

CPC分类号： G06F11/263 ,  H04L43/50

摘要： A system and method for validating packet classification within an input/output device or component. Based on a target DMA engine within the device, and a protocol path for testing the DMA engine, sets of packet attributes are generated and used to format packets for input to the device. The output of the device is examined to determine if the correct DMA engine was used within the device. The DMA policy specifying which DMA engine to use for a particular packet configuration or set of protocol attributes can be dynamically replaced or modified without halting the validation process.

摘要翻译： 一种用于在输入/输出设备或组件内验证分组分类的系统和方法。 基于设备内的目标DMA引擎和用于测试DMA引擎的协议路径，生成数据包属性集，并用于格式化数据包以便输入到设备。 检查器件的输出以确定器件中是否使用正确的DMA引擎。 指定用于特定数据包配置或协议属性集的DMA引擎的DMA策略可以动态替换或修改，而不会停止验证过程。

公开(公告)号：US08078928B2

公开(公告)日：2011-12-13

申请号：US11974413

申请日：2007-10-12

申请人： Arvind Srinivasan ,  Rahoul Puri

发明人： Arvind Srinivasan ,  Rahoul Puri

IPC分类号： G06F11/00

CPC分类号： H04L43/50

摘要： A system and method for verifying the transmit path of an input/output device such as a network interface circuit. The device's operation with various different input sources (e.g., hosts, input buses) and output sources (e.g., output buses, networks) is modeled in a verification layer that employs multiple queues to simulate receipt of input data, submission to an output port and transmission from the device. Call backs are employed to signal completion of events related to receipt of data at the device and modeling of data processing within the verification layer. As call backs are resolved, corresponding tasks are executed to advance the processing of the data through the verification layer. A device-specific algorithm is executed in the verification layer to predict the ordering of output from the device, and that output is compared to the predicted output by a transmission checker.

摘要翻译： 一种用于验证诸如网络接口电路的输入/输出设备的发送路径的系统和方法。 该设备在各种不同的输入源（例如，主机，输入总线）和输出源（例如，输出总线，网络）中的操作被建模在验证层中，该验证层采用多个队列来模拟输入数据的接收，提交到输出端口 从设备传输。 采用回叫信号来完成与设备上的数据接收有关的事件以及验证层内的数据处理建模。 随着回叫的解决，相应的任务被执行以通过验证层来推进对数据的处理。 在验证层中执行特定于设备的算法来预测来自设备的输出的顺序，并且将该输出与传输检查器的预测输出进行比较。

公开(公告)号：US07706289B2

公开(公告)日：2010-04-27

申请号：US11967225

申请日：2007-12-30

申请人： Rahoul Puri ,  Arvind Srinivasan ,  Saranga P. Pogula

发明人： Rahoul Puri ,  Arvind Srinivasan ,  Saranga P. Pogula

IPC分类号： G06F9/445

CPC分类号： G06F11/263 ,  H04L43/50

摘要： A system and method for validating packet classification within an input/output device or component. Based on a target DMA engine within the device, and a protocol path for testing the DMA engine, sets of packet attributes are generated and used to format packets for input to the device. The output of the device is examined to determine if the correct DMA engine was used within the device. The DMA policy specifying which DMA engine to use for a particular packet configuration or set of protocol attributes can be dynamically replaced or modified without halting the validation process.

摘要翻译： 一种用于在输入/输出设备或组件内验证分组分类的系统和方法。 基于设备内的目标DMA引擎和用于测试DMA引擎的协议路径，生成数据包属性集，并用于格式化数据包以便输入到设备。 检查器件的输出以确定器件中是否使用正确的DMA引擎。 指定用于特定数据包配置或协议属性集的DMA引擎的DMA策略可以动态替换或修改，而不会停止验证过程。

公开(公告)号：US20090100297A1

公开(公告)日：2009-04-16

申请号：US11974414

申请日：2007-10-12

申请人： Arvind Srinivasan ,  Rahoul Puri

发明人： Arvind Srinivasan ,  Rahoul Puri

IPC分类号： G06F11/00

CPC分类号： G06F11/277

摘要： A system and method for verifying the receive path of an input/output device such as a network interface circuit. The device's operation with various different input sources (e.g., networks) and output sources (e.g., hosts, host buses) is modeled in a verification layer that employs multiple queues to simulate receipt of packets, calculation of destination addresses and storage of the packet data by the device. Call backs are employed to signal completion of events related to storage of packet data by the device and modeling of data processing within the verification layer. Processing of tokens within the verification layer to mimic the device's processing of corresponding packets is performed according to a dynamic DMA policy modeled on the device's policy. The policy is dynamic and can be updated or replaced during verification without interrupting the verification process.

摘要翻译： 一种用于验证诸如网络接口电路的输入/输出设备的接收路径的系统和方法。 该设备利用各种不同的输入源（例如，网络）和输出源（例如，主机，主机总线）的操作被建模在采用多个队列来模拟分组的接收，计算目的地址和分组数据的存储的验证层 通过设备。 采用回叫信号来完成与设备的分组数据的存储相关的事件以及验证层内数据处理的建模。 根据设备策略建模的动态DMA策略，对验证层内的令牌进行处理以模拟设备对相应数据包的处理。 该策略是动态的，可以在验证过程中进行更新或替换，而不会中断验证过程。