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1.发明申请Techniques for integrated circuit clock signal manipulation to facilitate functional and speed test 有权集成电路时钟信号操作技术，便于功能和速度测试公开(公告)号：US20080288804A1
公开(公告)日：2008-11-20
申请号：US11750275
申请日：2007-05-17
申请人： Atchyuth Gorti , Tendy The , Daniel W. Bailey , Bill K.C. Kwan
发明人： Atchyuth Gorti , Tendy The , Daniel W. Bailey , Bill K.C. Kwan
IPC分类号： G06F1/12
CPC分类号： G01R31/31727
摘要： An integrated circuit (1600) includes a debug module (1602) and a clock generator (1610). The debug module (1602) is configured to receive a test pattern and provide a mode signal based on the test pattern. The clock generator (1610) includes a first clock input configured to receive a first clock signal, a second clock input configured to receive a second clock signal, and a mode input configured to receive the mode signal. The first and second clock signals are out of phase and have the same clock frequency. The clock generator (1610) is configured to provide a generated clock signal whose effective frequency is based on the first and second clock signals and the mode signal.
摘要翻译： 集成电路（1600）包括调试模块（1602）和时钟发生器（1610）。 调试模块（1602）被配置为接收测试模式并且基于测试模式提供模式信号。 时钟发生器（1610）包括被配置为接收第一时钟信号的第一时钟输入，被配置为接收第二时钟信号的第二时钟输入和被配置为接收模式信号的模式输入。 第一和第二时钟信号是相位不同的，具有相同的时钟频率。 时钟发生器（1610）被配置为提供其有效频率基于第一和第二时钟信号和模式信号的生成的时钟信号。
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2.发明授权Techniques for integrated circuit clock signal manipulation to facilitate functional and speed test 有权集成电路时钟信号操作技术，便于功能和速度测试公开(公告)号：US07681099B2
公开(公告)日：2010-03-16
申请号：US11750275
申请日：2007-05-17
申请人： Atchyuth Gorti , Tendy The , Daniel W. Bailey , Bill K. C. Kwan
发明人： Atchyuth Gorti , Tendy The , Daniel W. Bailey , Bill K. C. Kwan
CPC分类号： G01R31/31727
摘要： An integrated circuit (1600) includes a debug module (1602) and a clock generator (1610). The debug module (1602) is configured to receive a test pattern and provide a mode signal based on the test pattern. The clock generator (1610) includes a first clock input configured to receive a first clock signal, a second clock input configured to receive a second clock signal, and a mode input configured to receive the mode signal. The first and second clock signals are out of phase and have the same clock frequency. The clock generator (1610) is configured to provide a generated clock signal whose effective frequency is based on the first and second clock signals and the mode signal.
摘要翻译： 集成电路（1600）包括调试模块（1602）和时钟发生器（1610）。 调试模块（1602）被配置为接收测试模式并且基于测试模式提供模式信号。 时钟发生器（1610）包括被配置为接收第一时钟信号的第一时钟输入，被配置为接收第二时钟信号的第二时钟输入和被配置为接收模式信号的模式输入。 第一和第二时钟信号是相位不同的，具有相同的时钟频率。 时钟发生器（1610）被配置为提供其有效频率基于第一和第二时钟信号和模式信号的生成的时钟信号。
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