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公开(公告)号：US20120275242A1
公开(公告)日：2012-11-01
申请号：US13543495
申请日：2012-07-06
CPC分类号： G11C11/4091 , Y10T307/50
摘要： Some embodiments regard a circuit comprising a memory cell, a first data line, a second data line, a sensing circuit coupled to the first data line and the second data line, a node selectively coupled to at least three voltage sources via at least three respective switches, a fourth switch, and a fifth switch. A first voltage source is configured to supply a retention voltage to the node via a first switch. A second voltage source is configured to supply a ground reference voltage to the node via a second switch, and a third voltage source is configured to supply a reference voltage to the node via a third switch. The fourth switch and fifth switch are configured to receive a respective first control signal and second control signal and to pass a voltage at the node to the respective first data line and second data line.
摘要翻译： 一些实施例涉及包括存储器单元，第一数据线，第二数据线，耦合到第一数据线和第二数据线的感测电路的电路，经由至少三个相应的选择性地耦合到至少三个电压源的节点 开关，第四开关和第五开关。 第一电压源被配置为经由第一开关向节点提供保持电压。 第二电压源被配置为经由第二开关向节点提供接地参考电压，并且第三电压源被配置为经由第三开关向节点提供参考电压。 第四开关和第五开关被配置为接收相应的第一控制信号和第二控制信号，并将节点处的电压传递到相应的第一数据线和第二数据线。
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公开(公告)号：US20120307580A1
公开(公告)日：2012-12-06
申请号：US13118956
申请日：2011-05-31
IPC分类号： G11C7/12
CPC分类号： G11C11/4094
摘要： A circuit comprises a set of pre-charge and equalization devices, a control signal line, and a word line. The set of pre-charge and equalization devices is configured to pre-charge and equalize a pair of data lines. The control signal line is configured to control the pre-charge and equalization devices. The word line is configured to electrically couple a memory cell to a data line of the pair of data lines. A first voltage value provided to the control signal line is from a first voltage source different from a second voltage source that generates a second voltage value for the word line.
摘要翻译： 电路包括一组预充电和均衡装置，控制信号线和字线。 该组预充电和均衡装置被配置为对一对数据线进行预充电和均衡。 控制信号线被配置为控制预充电和均衡装置。 字线被配置为将存储器单元电耦合到该对数据线的数据线。 提供给控制信号线的第一电压值来自不同于产生字线的第二电压值的第二电压源的第一电压源。
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公开(公告)号：US20120256681A1
公开(公告)日：2012-10-11
申请号：US13082918
申请日：2011-04-08
IPC分类号： G05F3/02
摘要： A charge pump circuit comprises a first node, a second node, and at least one capacitance stage coupled between the first node and the second node. Capacitance stages of the at least one capacitance stage are coupled in series. A capacitance stage of the at least one capacitance stage includes a capacitive device and a voltage limiter coupled in parallel with the capacitor. The voltage limiter is configured to limit a voltage dropped across the capacitor. The capacitive device and the voltage limiter are configured such that a first current flowing through a first branch having the voltage limiter is more than a second current flowing through a second branch having the capacitive device.
摘要翻译： 电荷泵电路包括第一节点，第二节点和耦合在第一节点和第二节点之间的至少一个电容级。 至少一个电容级的电容级串联耦合。 至少一个电容级的电容级包括电容器件和与电容器并联耦合的限压器。 电压限制器被配置为限制电容器下降的电压。 电容性器件和限压器被配置为使流过具有限压器的第一支路的第一电流大于流过具有电容器件的第二支路的第二电流。
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公开(公告)号：US20120032511A1
公开(公告)日：2012-02-09
申请号：US12852638
申请日：2010-08-09
IPC分类号： H02J1/00
CPC分类号： G11C11/4091 , Y10T307/50
摘要： Some embodiments regard a circuit comprising a memory cell, a first data line, a second data line, a sensing circuit coupled to the first data line and the second data line, a node selectively coupled to at least three voltage sources via at least three respective switches, a fourth switch, and a fifth switch. A first voltage source is configured to supply a retention voltage to the node via a first switch. A second voltage source is configured to supply a ground reference voltage to the node via a second switch, and a third voltage source is configured to supply a reference voltage to the node via a third switch. The fourth switch and fifth switch are configured to receive a respective first control signal and second control signal and to pass a voltage at the node to the respective first data line and second data line.
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公开(公告)号：US20130016576A1
公开(公告)日：2013-01-17
申请号：US13183154
申请日：2011-07-14
CPC分类号： G11C11/4094 , G11C11/4091 , G11C11/4097
摘要： A circuit comprises a plurality of memory cells, a word line, a plurality of pairs of bit lines, a pre-charge and equalization device, a column select device, and a sense amplifier. The word line is configured to control the plurality of memory cells. Each pair of bit lines of the plurality of pairs of bit lines corresponds to a memory cell of the plurality of memory cells and is coupled to a pair of switches. The sense amplifier is coupled to the plurality of pairs of bit lines, the pre-charge and equalization device, and the column select device.
摘要翻译： 电路包括多个存储器单元，字线，多对位线，预充电和均衡器件，列选择器件和读出放大器。 字线被配置为控制多个存储单元。 多对位线对中的每对位线对应于多个存储单元的存储单元，并且耦合到一对开关。 读出放大器耦合到多对位线，预充电和均衡器件以及列选择器件。
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公开(公告)号：US20130215695A1
公开(公告)日：2013-08-22
申请号：US13399993
申请日：2012-02-17
IPC分类号： G11C29/00
CPC分类号： G11C29/00 , G06F11/1048 , G11C29/4401 , G11C29/808
摘要： A memory array has a plurality of rows. Each row of the plurality of rows includes a plurality of memory words. Each first bit of a plurality of first bits is associated with a memory word of the each row. A state of the each first bit indicates whether the memory word associated the each first bit has had an error. Each redundancy row of a plurality of redundancy rows includes a plurality of redundancy words. Each redundancy word is associated with a memory word. Each second bit of a plurality of second bits is associated with a redundancy word of the plurality of redundancy words of the each row of the plurality of redundancy rows. A state of the each second bit indicates whether the redundancy word associated with the each second bit has had an error.
摘要翻译： 存储器阵列具有多个行。 多行中的每行包括多个存储字。 多个第一比特的每个第一比特与每一行的存储器字相关联。 每个第一位的状态指示与每个第一位相关联的存储器字是否具有错误。 多个冗余行的每个冗余行包括多个冗余字。 每个冗余字与存储器字相关联。 多个第二比特的每个第二比特与多个冗余行的每行的多个冗余字的冗余字相关联。 每个第二位的状态指示与每个第二位相关联的冗余字是否具有错误。
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公开(公告)号：US20110041016A1
公开(公告)日：2011-02-17
申请号：US12849157
申请日：2010-08-03
CPC分类号： G11C29/42 , G06F11/1048 , G11C29/44 , G11C29/4401 , G11C29/76 , G11C2029/0401 , G11C2029/0409 , G11C2029/0411 , G11C2029/1208
摘要： Redundancy including extra rows and/or columns of memory cells is added to the memory, and ECC parity is used to detect errors. When an error occurs at a location the first time, it is assumed to be a soft error, the data is corrected in this location, and the address of the erroneous cell (e.g., the failed address) is stored in a list. When another error occurs, it is determined whether its failed address is on the stored list. If it is not, then the error is again assumed to be a soft error, the data at this location is corrected, and the failed address is added to the stored address list, etc. If, however, the failed address is already in the stored failed address list, the error is considered either a latent error or VTR, and is repaired on the fly using on-chip redundancy.
摘要翻译： 包含额外的行和/或存储单元列的冗余被添加到存储器中，并且使用ECC奇偶校验来检测错误。 当第一次在某个位置发生错误时，假定为软错误，在该位置校正数据，并将错误小区的地址（例如，故障地址）存储在列表中。 当发生另一个错误时，确定其失败的地址是否在存储的列表上。 如果不是，则再次假定该错误是软错误，该位置处的数据被更正，并且将失败的地址添加到存储的地址列表等中。然而，如果失败的地址已经在 存储失败的地址列表，该错误被认为是潜在错误或VTR，并且使用片上冗余进行即时修复。
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