公开(公告)号：US11114132B2

公开(公告)日：2021-09-07

申请号：US17125011

申请日：2020-12-17

申请人： Audigo Labs Inc.

发明人： Brian Chasson Gomberg ,  Armen Alan Nazarian ,  Kenneth Aaron Murphy

IPC分类号： G11B27/10 ,  H04N5/765 ,  H04W56/00

摘要： A system and method for synchronizing clocks including synchronizing a first clock to a second clock, the first clock associated with a first device, the first device associated with a first device type, the second clock associated with a second device, the second device associated with a second device type; subsequent to synchronizing the first clock to the second clock, synchronizing a third clock to the first clock, where the third clock is associated with a third device, the third device associated with the first device type; synchronizing the second clock to a fourth clock, the fourth clock associated with a fourth device, the fourth device associated with a third device type; subsequent to synchronizing the second clock to the fourth clock, resynchronizing the first clock to the second clock; and subsequent to resynchronizing the first clock to the second clock, resynchronizing the third clock to the first clock.

公开(公告)号：US20220148623A1

公开(公告)日：2022-05-12

申请号：US17408231

申请日：2021-08-20

申请人： Audigo Labs Inc.

发明人： Brian Chasson Gomberg ,  Armen Alan Nazarian ,  Kenneth Aaron Murphy

IPC分类号： G11B27/10 ,  H04N5/765 ,  H04W56/00

摘要： A system and method for synchronizing clocks including synchronizing a first clock to a second clock, the first clock associated with a first device, the first device associated with a first device type, the second clock associated with a second device, the second device associated with a second device type; subsequent to synchronizing the first clock to the second clock, synchronizing a third clock to the first clock, where the third clock is associated with a third device, the third device associated with the first device type; synchronizing the second clock to a fourth clock, the fourth clock associated with a fourth device, the fourth device associated with a third device type; subsequent to synchronizing the second clock to the fourth clock, resynchronizing the first clock to the second clock; and subsequent to resynchronizing the first clock to the second clock, resynchronizing the third clock to the first clock.

公开(公告)号：US11621023B2

公开(公告)日：2023-04-04

申请号：US17408231

申请日：2021-08-20

申请人： Audigo Labs Inc.

发明人： Brian Chasson Gomberg ,  Armen Alan Nazarian ,  Kenneth Aaron Murphy

IPC分类号： G11B27/10 ,  H04N5/765 ,  H04W56/00

摘要： A system and method for synchronizing clocks including synchronizing a first clock to a second clock, the first clock associated with a first device, the first device associated with a first device type, the second clock associated with a second device, the second device associated with a second device type; subsequent to synchronizing the first clock to the second clock, synchronizing a third clock to the first clock, where the third clock is associated with a third device, the third device associated with the first device type; synchronizing the second clock to a fourth clock, the fourth clock associated with a fourth device, the fourth device associated with a third device type; subsequent to synchronizing the second clock to the fourth clock, resynchronizing the first clock to the second clock; and subsequent to resynchronizing the first clock to the second clock, resynchronizing the third clock to the first clock.

公开(公告)号：US20210183409A1

公开(公告)日：2021-06-17

申请号：US17125011

申请日：2020-12-17

申请人： Audigo Labs Inc.

发明人： Brian Chasson Gomberg ,  Armen Alan Nazarian ,  Kenneth Aaron Murphy

IPC分类号： G11B27/10 ,  H04W56/00 ,  H04N5/765

摘要： A system and method for synchronizing clocks including synchronizing a first clock to a second clock, the first clock associated with a first device, the first device associated with a first device type, the second clock associated with a second device, the second device associated with a second device type; subsequent to synchronizing the first clock to the second clock, synchronizing a third clock to the first clock, where the third clock is associated with a third device, the third device associated with the first device type; synchronizing the second clock to a fourth clock, the fourth clock associated with a fourth device, the fourth device associated with a third device type; subsequent to synchronizing the second clock to the fourth clock, resynchronizing the first clock to the second clock; and subsequent to resynchronizing the first clock to the second clock, resynchronizing the third clock to the first clock.