公开(公告)号：US07577881B1

公开(公告)日：2009-08-18

申请号：US11431219

申请日：2006-05-09

申请人： Avadhani Shridhar ,  Abhijit Shah

发明人： Avadhani Shridhar ,  Abhijit Shah

IPC分类号： G11C29/00

CPC分类号： H03M13/2732 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/23 ,  H04L1/0071

摘要： A modem configured to couple to a communication medium for establishing a communication channel thereon. The modem includes an interleaver component configurable as to interleaver parameters ‘I, D’ corresponding to block length and depth respectively. An interleaver memory buffers the communication channel. An interleaver controller controls writing to and reading from the memory of successive data elements of the communication channel with a quantity ‘I’ pairs of write and read pointers. Each pair or write and read pointers identifies memory locations corresponding with an input and output respectively of an associated one of ‘I’ virtual first-in-first-out (‘v-FIFO’) buffers in the memory. Control of the pointers required to read out the stored data elements in interleaved fashion is limited to shifting all pointers uniformly by one address block in each interleaver block cycle, which simplifies pointer management.

摘要翻译： 配置成耦合到通信介质以在其上建立通信信道的调制解调器。 调制解调器包括可配置为分别对应于块长度和深度的交织器参数“I”的交织器组件。 交织器存储器缓冲通信信道。 交织器控制器控制用数量“I”对写入和读取指针对通信信道的连续数据元素的存储器进行写入和读取。 每对或写入和读取指针分别标识与输入和输出相对应的存储器位置，该存储单元分别与存储器中的“I”虚拟先进先出（'v-FIFO'）缓冲器相关联。 以交错方式读取存储的数据元素所需的指针的控制被限制为在每个交织器块周期中将所有指针均匀地移位一个地址块，这简化了指针管理。