公开(公告)号：US06366937B1

公开(公告)日：2002-04-02

申请号：US09267899

申请日：1999-03-11

申请人： Avadhani Shridhar ,  Arindam Saha

发明人： Avadhani Shridhar ,  Arindam Saha

IPC分类号： G06F1714

CPC分类号： G06F9/30014 ,  G06F9/30036 ,  G06F17/142

摘要： A system and method that implement a butterfly operation for a fast fourier transform operation in a processor using a matrix-vector-multiply instruction. A first set of inputs to the butterfly operation are defined as r1+j i1 and r2+j i2, and a twiddle factor Wn is defined as Wn=e−j2&pgr;/N=cos(2&pgr;/N)−j sin(2&pgr;/N)=a+jb. The butterfly operation stores r1, i1, r2 and i2 in a first set of registers and stores the twiddle factor in matrix registers. The matrix-vector-multiply instruction is executed between the matrix registers and the first set of registers.

摘要翻译： 一种在使用矩阵向量乘法指令的处理器中实现用于快速傅里叶变换操作的蝶形运算的系统和方法。 蝶形运算的第一组输入被定义为r1 + ji1和r2 + j i2，旋转因子Wn定义为Wn = e-j2pi / N = cos（2pi / N）-jsin（2pi / N）= a + jb。 蝶形运算将r1，i1，r2和i2存储在第一组寄存器中，并将旋转因子存储在矩阵寄存器中。 矩阵向量乘法指令在矩阵寄存器和第一组寄存器之间执行。

公开(公告)号：US20130051488A1

公开(公告)日：2013-02-28

申请号：US13403956

申请日：2012-02-23

申请人： Avadhani Shridhar ,  Kevin Fisher

发明人： Avadhani Shridhar ,  Kevin Fisher

IPC分类号： H04B15/00

CPC分类号： H04B3/32 ,  H04B3/487 ,  H04M11/062

摘要： A DSL system performs crosstalk cancellation using a plurality of vectoring cancellation chips that are partitioned into two or more groups based on DSL victim lines or DSL disturber lines or DSL tones. Embodiments of the invention include both single-criteria and double-criteria partitioning methods. In double-criteria embodiments, the vectoring cancellation VCE chips are first partitioned into two or more victim DSL line groups and then in each group the VCE chips are further partitioned by disturber DSL line processing. Alternately, the vectoring cancellation VCE chips are first partitioned into two or more disturber DSL line groups and then within each group further partitioned by victim DSL line processing. By partitioning the computation as described herein, the invention reduces the bandwidth and the number of links between the chips, without too much co-ordination complexity. This allows crosstalk cancellation across larger vectored groups.

摘要翻译： DSL系统使用基于DSL受害线或DSL干扰线或DSL音调将其划分为两个或多个组的多个向量消除芯片来执行串扰消除。 本发明的实施例包括单一标准和双准则划分方法。 在双标准实施例中，向量消除VCE码片首先划分成两个或多个受害DSL线路组，然后在每个组中，VCE码片进一步被干扰DSL线路处理分割。 或者，矢量取消VCE芯片首先划分成两个或更多个干扰DSL线路组，然后在每个组内进一步被受害DSL线路处理划分。 通过如本文所述分割计算，本发明降低了芯片之间的带宽和链路数量，而没有太多的协调复杂性。 这允许跨较大矢量组的串扰消除。

公开(公告)号：US07315571B1

公开(公告)日：2008-01-01

申请号：US09837914

申请日：2001-04-18

申请人： Sam Heidari ,  Behrooz Rezvani ,  Raminder S. Bajwa ,  Jacky Chow ,  Avadhani Shridhar ,  Dale Smith ,  John Gevargiz ,  Saman Behtash

发明人： Sam Heidari ,  Behrooz Rezvani ,  Raminder S. Bajwa ,  Jacky Chow ,  Avadhani Shridhar ,  Dale Smith ,  John Gevargiz ,  Saman Behtash

IPC分类号： H04B1/38

CPC分类号： H04L27/2628 ,  H04L5/0042 ,  H04L5/0044 ,  H04L5/0064 ,  H04L27/0002 ,  H04L27/265 ,  H04M11/062

摘要： A transceiver for communicating a multi-tone modulated communication channel on a subscriber line. The transceiver includes: a digital signal processor (DSP) with a Fourier transform module and an analog front end (AFE). The DSP determines an available range of frequencies on the subscriber line and expands or contracts the tone spacing of each of a fixed number “N” of tones accordingly by decreasing or increasing the processing interval associated with the Fourier transform of each tone set. The AFE performs digital-to-analog conversion of the multi-tone modulated communication channel at rates compatible with the processing interval of the Fourier transform module; whereby the range of frequencies spanned by the modulated tones on the subscriber line conforms to the available of frequencies on the subscriber line.

摘要翻译： 用于在用户线路上传送多音调调制通信信道的收发器。 收发器包括：具有傅立叶变换模块和模拟前端（AFE）的数字信号处理器（DSP）。 DSP确定用户线路上的可用频率范围，并通过减少或增加与每个音调集合的傅里叶变换相关联的处理间隔来相应地扩展或收缩固定数量“N”个音调中的每一个的音调间隔。 AFE以与傅里叶变换模块的处理间隔兼容的速率执行多音调调制通信信道的数模转换; 由此用户线路上的调制音调跨越的频率范围符合用户线上的可用频率。

公开(公告)号：US06940807B1

公开(公告)日：2005-09-06

申请号：US09699193

申请日：2000-10-26

申请人： Behrooz Rezvani ,  Avadhani Shridhar ,  Raminder S. Bajwa ,  Tiruvur R. Ramesh ,  Masoud Eskandari ,  Firooz Massoudi ,  Sam Heidari ,  Omprakash S. Sarmaru ,  Sridhar Begur

发明人： Behrooz Rezvani ,  Avadhani Shridhar ,  Raminder S. Bajwa ,  Tiruvur R. Ramesh ,  Masoud Eskandari ,  Firooz Massoudi ,  Sam Heidari ,  Omprakash S. Sarmaru ,  Sridhar Begur

IPC分类号： H04J11/00

CPC分类号： G06F17/142 ,  H04L27/2628 ,  H04L27/265

摘要： The current invention provides a DSP which accommodates multiple current X-DSL protocols and is further configurable to support future protocols. The DSP is implemented with shared and dedicated hardware components on both the transmit and receive paths. The DSP implements both the discrete Fourier transform (DFT) and inverse discrete Fourier transform (IDFT) portions across a wide range of sample sizes and X-DSL protocols. Multiple channels, each with varying ones of the X-DSL protocols can be handled in the same session. The DSP offers the speed associated with hardware implementation of the transforms and the flexibility of a software only implementation. Traffic flow is regulated in the chip using a packet based schema in which each packet is associated with a specific channel of upstream and downstream data. Header and control information in each packet is used to govern the processing of each packet as it moves along either the transmit path or receive path. The DSP of the current invention may advantageously be utilized in fields other than communications, such as: medical and other imaging, seismic analysis, radar and other military applications, pattern recognition, signal processing etc. The present invention provides a signal processing architecture that supports scalability of CO/DLC/ONU resources, and allows a significantly more flexible hardware response to the evolving X-DSL standards without over committing of hardware resources. As standards evolve hardware may be reconfigured to support the new standards.

摘要翻译： 本发明提供一种DSP，其容纳多个当前的X-DSL协议，并且可进一步配置以支持未来的协议。 DSP在传输和接收路径上都具有共享和专用硬件组件。 DSP在宽范围的采样大小和X-DSL协议上实现离散傅立叶变换（DFT）和离散傅立叶逆变换（IDFT）部分。 每个具有不同的X-DSL协议的多个信道可以在同一个会话中处理。 DSP提供与转换的硬件实现相关的速度和仅用于软件的实现的灵活性。 使用基于分组的模式在芯片中调整流量流，其中每个分组与上游和下游数据的特定信道相关联。 每个数据包中的报头和控制信息用于控制每个数据包沿着发送路径或接收路径移动时的处理。 本发明的DSP可有利地用于通信以外的领域，例如：医疗和其他成像，地震分析，雷达和其他军事应用，模式识别，信号处理等。本发明提供一种信号处理架构，其支持 CO / DLC / ONU资源的可扩展性，并且允许对演进的X-DSL标准的显着更灵活的硬件响应，而不必超过硬件资源。 随着标准的发展，硬件可能被重新配置以支持新的标准。

公开(公告)号：US5727194A

公开(公告)日：1998-03-10

申请号：US478438

申请日：1995-06-07

申请人： Avadhani Shridhar ,  Kenichi Nitta

发明人： Avadhani Shridhar ,  Kenichi Nitta

IPC分类号： G06F9/32 ,  G06F9/45 ,  G06F9/30

CPC分类号： G06F8/447 ,  G06F9/325

摘要： A repeat-bit based system and method for executing zero overhead loops, or repeat loops, in an information processing chip that does not require a repeat end register or a dedicated comparator. Executing repeat loops requires a processor to iterate N times a code fragment of loop instructions. All systems providing this capability must know when to refetch the first loop instruction at the end of a repeat. To do this, the present invention adds a repeat bit to the processor's instruction set. This bit is set by the assembler/compiler that generates the executable code fragment comprising the repeat loop. Where the repeat loop includes plural instructions, the assembler sets the repeat bit of the penultimate loop instruction. As each loop instruction is fetched, decoded and executed, the decoder detects the repeat bit and passes it to loop control circuitry. If the code fragment has not been iterated N times and the repeat bit is set, the program counter (PC) is loaded with the address of the first repeat loop instruction, which is refetched. Otherwise, the PC is incremented and the next instruction is fetched. Where the repeat loop has a single instruction, a nop instruction must be added after the instruction to be repeated. Two systems and methods for maintaining the repeat count are disclosed. The first requires a decrementor that decrements the repeat count from N each time the loop is iterated. Another replaces the decrementor with the PC incrementor, which increments the repeat counter from -N or -(N-1).

摘要翻译： 一种基于重复位的系统和方法，用于在不需要重复结束寄存器或专用比较器的信息处理芯片中执行零开销环路或重复循环。 执行重复循环需要处理器重复N次循环指令的代码片段。 提供此功能的所有系统必须知道在重复结束时何时重新获取第一个循环指令。 为此，本发明向处理器的指令集添加重复位。 该位由汇编器/编译器设置，生成包含重复循环的可执行代码段。 在重复循环包括多个指令的地方，汇编器设置倒数第二个循环指令的重复位。 当每个循环指令被取出，解码和执行时，解码器检测重复位并将其传递给环路控制电路。 如果代码片段没有被迭代N次并且重复位被设置，则程序计数器（PC）被加载有第一个重复循环指令的地址，这被重写。 否则，PC将递增，并取下一条指令。 在重复循环具有单个指令的情况下，必须在要重复的指令之后添加nop指令。 公开了用于维持重复计数的两种系统和方法。 第一个需要一个递减器，每次迭代循环时，从N减少重复计数。 另一个用PC增量器代替递减器，该增量器从-N或 - （N-1）增加重复计数器。

公开(公告)号：US20100002755A1

公开(公告)日：2010-01-07

申请号：US12459129

申请日：2009-06-25

申请人： Sam Heidari ,  Sivannarayana Nagireddi ,  Sigurd Schelstraete ,  Avadhani Shridhar

发明人： Sam Heidari ,  Sivannarayana Nagireddi ,  Sigurd Schelstraete ,  Avadhani Shridhar

IPC分类号： H04B1/38

CPC分类号： H04B3/542 ,  H04B2203/5408 ,  H04B2203/5445 ,  H04B2203/5454 ,  H04L5/0037 ,  H04L5/0064 ,  H04L5/0092 ,  H04L5/1438

摘要： A multi-tone modem with shared and discrete components forming a transmit path and a receive path configured to couple to a wired communication medium to communicate at least one multi-tone modulated communication channel thereon. The modem includes a multi-tone modulator component and a configurable frequency up converter component. The multi-tone modulator component is configured for multi-tone modulation and demodulation of a transmitted and received communication channel at a base band frequency range. The configurable frequency up converter component is coupled to the multi-tone modulator to selectably up convert the frequency range of the transmitted base band signal from the multi-tone modulator to that of a selected communication band and down convert received signals from the selected communication band to the base band for demodulation by the multi-tone modulator.

摘要翻译： 具有形成发送路径的共享和分立组件的多音调制解调器和被配置为耦合到有线通信介质以在其上通信至少一个多音调调制通信信道的接收路径。 调制解调器包括多音调制器组件和可配置的升频转换器组件。 多音调制器部件被配置为在基带频率范围内对发送和接收的通信信道进行多音调制和解调。 可配置的上变频器组件耦合到多音调制器以可选择地将来自多音调制器的发射基带信号的频率范围转换成所选择的通信频带的频率范围，并且将来自所选择的通信频带的接收信号 到基带以进行多音调制器的解调。

公开(公告)号：US07577881B1

公开(公告)日：2009-08-18

申请号：US11431219

申请日：2006-05-09

申请人： Avadhani Shridhar ,  Abhijit Shah

发明人： Avadhani Shridhar ,  Abhijit Shah

IPC分类号： G11C29/00

CPC分类号： H03M13/2732 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/23 ,  H04L1/0071

摘要： A modem configured to couple to a communication medium for establishing a communication channel thereon. The modem includes an interleaver component configurable as to interleaver parameters ‘I, D’ corresponding to block length and depth respectively. An interleaver memory buffers the communication channel. An interleaver controller controls writing to and reading from the memory of successive data elements of the communication channel with a quantity ‘I’ pairs of write and read pointers. Each pair or write and read pointers identifies memory locations corresponding with an input and output respectively of an associated one of ‘I’ virtual first-in-first-out (‘v-FIFO’) buffers in the memory. Control of the pointers required to read out the stored data elements in interleaved fashion is limited to shifting all pointers uniformly by one address block in each interleaver block cycle, which simplifies pointer management.

摘要翻译： 配置成耦合到通信介质以在其上建立通信信道的调制解调器。 调制解调器包括可配置为分别对应于块长度和深度的交织器参数“I”的交织器组件。 交织器存储器缓冲通信信道。 交织器控制器控制用数量“I”对写入和读取指针对通信信道的连续数据元素的存储器进行写入和读取。 每对或写入和读取指针分别标识与输入和输出相对应的存储器位置，该存储单元分别与存储器中的“I”虚拟先进先出（'v-FIFO'）缓冲器相关联。 以交错方式读取存储的数据元素所需的指针的控制被限制为在每个交织器块周期中将所有指针均匀地移位一个地址块，这简化了指针管理。

公开(公告)号：US20090049347A1

公开(公告)日：2009-02-19

申请号：US12228972

申请日：2008-08-18

申请人： Avadhani Shridhar ,  Sam Heidari

发明人： Avadhani Shridhar ,  Sam Heidari

IPC分类号： G06F11/00

CPC分类号： H04L5/1446 ,  H04L1/0003 ,  H04L1/0059 ,  H04L1/203 ,  H04L1/206 ,  H04L5/1469 ,  H04L27/2647 ,  H04L27/2689

摘要： A transceiver with a plurality of components coupled to one another to form a transmit path and a receive path for multi-tone modulation of user data across a communication medium. The transceiver includes a framer and a deframer. The framer is configured to momentarily suspend framing of user data before processing bits associated with tones targeted for reference data transport and injects the pre-agreed reference pattern therein, after which framing of user data resumes. The deframer is configured to momentarily suspend deframing of received user data bits before processing bits associated with tones targeted for transport of pre-agreed reference data and extracts the received reference bits thereof for comparison with the corresponding pre-agreed reference bits to determine errors therein, after which deframing of user data resumes.

摘要翻译： 具有多个组件的收发器，彼此耦合以形成用于通过通信介质的用户数据的多音调制的发送路径和接收路径。 收发器包括一个成帧器和一个deframer。 成帧器被配置为在处理与针对参考数据传输的音调相关联的位之前暂时停止用户数据的成帧，并在其中注入预先约定的参考模式，之后恢复用户数据的构图。 解帧器被配置为在处理与预先约定的参考数据的传输的目标的音调相关联的位之前暂时停止所接收的用户数据位的解帧，并提取其接收到的参考比特以与对应的预先约定的参考比特进行比较以确定其中的错误， 之后恢复用户数据的清除。

公开(公告)号：US20060101432A1

公开(公告)日：2006-05-11

申请号：US11221239

申请日：2005-09-06

申请人： John Simons ,  Avadhani Shridhar

发明人： John Simons ,  Avadhani Shridhar

IPC分类号： G06F9/45

CPC分类号： G06F8/423

摘要： A assembler extended instruction set architecture ISA is formed from a current ISA to which is added new instructions. Assembly of source code listing of a mixture of current and new assembly language instructions is accomplished by preprocessing the source code to create a temporary file that contains the old instructions and data directives for each of the new assembly instructions that have, as the data arguments, the object code equivalent of such new instruction. The temporary file is then applied to the old assembler to produce, for each of the old assembly language instructions, the corresponding object code. The result, after linking, is an executable, machine language program for the new ISA.

公开(公告)号：US06937616B1

公开(公告)日：2005-08-30

申请号：US09620779

申请日：2000-07-21

申请人： Behrooz Rezvani ,  Sam Heidari ,  Avadhani Shridhar ,  Omprakash S. Samaru ,  Firooz Massoudi

发明人： Behrooz Rezvani ,  Sam Heidari ,  Avadhani Shridhar ,  Omprakash S. Samaru ,  Firooz Massoudi

IPC分类号： H04J3/22 ,  H04L12/28 ,  H04M11/06

CPC分类号： H04L12/2883 ,  H04L12/2856 ,  H04M11/062

摘要： A method and apparatus for digital subscriber line (xDSL) communications between one or more digital signal processors (DSPs) and analog front ends (AFEs) each coupled to corresponding subscriber line(s). The apparatus transports channels of data between subscribers and the DSP(s). The apparatus includes a bus for the transport of digital data, a DSP AFE interfaces. The DSP interfaces couples the DSP to the bus. The DSP interface accepts downstream channels of digital data from the DSP and transmits packets each associated with a corresponding one of the downstream channels to the bus. Each of the packets identifies a targeted AFEs coupled to a selected one of the subscriber lines. The AFE interfaces each couple an associated one of the AFEs to the bus. Each of the AFE interfaces transmits selected packets to a selected one of the subscriber lines for the transport to the subscriber.

摘要翻译： 一种用于一个或多个数字信号处理器（DSP）和模拟前端（AFE）之间的数字用户线（xDSL）通信的方法和装置，每个耦合到对应的用户线路。 该设备在订户和DSP之间传输数据信道。 该装置包括用于传输数字数据的总线，DSP AFE接口。 DSP接口将DSP耦合到总线。 DSP接口接收来自DSP的数字数据的下行信道，并且将与相应的一个下行信道相关联的分组发送到总线。 每个分组识别耦合到所选择的一个用户线路的目标AFE。 AFE接口将每个AFE接口中的一个耦合到总线。 每个AFE接口将所选择的分组传送到所选择的一个用户线，以便传输给用户。