公开(公告)号：US20140270028A1

公开(公告)日：2014-09-18

申请号：US13800557

申请日：2013-03-13

Applicant: Avnera Corporation

Inventor： Samuel J. Peters, II ,  Eric P. Etheridge ,  Victor Lee Hanson ,  Alexander C. Stange

IPC: H04L7/027

CPC classification number: H04L7/027 ,  G06F13/4295 ,  H04L7/0029 ,  H04L7/02

Abstract: A system and a technique for recovering data from an input data stream without synchronization of an input sampling circuit to the input data stream determines a count of incoming samples (or frames) without generating a signal that is frequency-locked to the input data stream. A first clock is generated comprising a frequency that is greater than or equal to an expected frequency of the input data stream. A sample count is incremented in response to a sample received in the input data stream, and is decremented in response to a second clock signal. The second clock is generated the first clock signal by passing the first clock signal if the sample count of the sample counter does not equal a predetermined sample count value and by blocking the first clock signal if the sample count equals the predetermined sample count value.

Abstract translation: 用于从输入数据流中恢复数据而不输入输入采样电路与输入数据流的同步的系统和技术确定输入采样（或帧）的计数，而不产生频率锁定到输入数据流的信号。 产生包括大于或等于输入数据流的预期频率的频率的第一时钟。 响应于在输入数据流中接收到的采样，采样计数递增，并且响应于第二时钟信号递减。 如果采样计数器的采样计数不等于预定采样计数值，并且如果采样计数等于预定采样计数值则阻塞第一时钟信号，则通过传递第一时钟信号来产生第二时钟信号。

公开(公告)号：US08848849B1

公开(公告)日：2014-09-30

申请号：US13800557

申请日：2013-03-13

Applicant: Avnera Corporation

Inventor： Samuel J. Peters ,  Eric P. Etheridge ,  Victor Lee Hanson ,  Alexander C. Stange

IPC: H04L7/02

CPC classification number: H04L7/027 ,  G06F13/4295 ,  H04L7/0029 ,  H04L7/02

Abstract: A system and a technique for recovering data from an input data stream without synchronization of an input sampling circuit to the input data stream determines a count of incoming samples (or frames) without generating a signal that is frequency-locked to the input data stream. A first clock is generated comprising a frequency that is greater than or equal to an expected frequency of the input data stream. A sample count is incremented in response to a sample received in the input data stream, and is decremented in response to a second clock signal. The second clock is generated the first clock signal by passing the first clock signal if the sample count of the sample counter does not equal a predetermined sample count value and by blocking the first clock signal if the sample count equals the predetermined sample count value.

Abstract translation: 用于从输入数据流中恢复数据而不输入输入采样电路与输入数据流的同步的系统和技术确定输入采样（或帧）的计数，而不产生频率锁定到输入数据流的信号。 产生包括大于或等于输入数据流的预期频率的频率的第一时钟。 响应于在输入数据流中接收到的采样，采样计数递增，并且响应于第二时钟信号递减。 如果采样计数器的采样计数不等于预定采样计数值，并且如果采样计数等于预定采样计数值则阻塞第一时钟信号，则通过传递第一时钟信号来产生第二时钟信号。